Hardware-accelerated real-time IP flow measurement method for multi-core architecture
A hardware-accelerated real-time IP flow measurement method for multi-core architecture was proposed. IP datagrams were captured at wire speed of OC-192 links by FPGA. Data records were load balanced to the corresponding core-affinitive buffer queues to each processor core at flow level. Multi-stage...
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | zho |
| Published: |
Editorial Department of Journal on Communications
2008-01-01
|
| Series: | Tongxin xuebao |
| Subjects: | |
| Online Access: | http://www.joconline.com.cn/thesisDetails?columnId=74652934&Fpath=home&index=0 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1850213784614862848 |
|---|---|
| author | ZHU Chao1 XIE Ying-ke1 WANG Jian-dong1 ZHAO Zi-li1 HAN Cheng-de1 |
| author_facet | ZHU Chao1 XIE Ying-ke1 WANG Jian-dong1 ZHAO Zi-li1 HAN Cheng-de1 |
| author_sort | ZHU Chao1 |
| collection | DOAJ |
| description | A hardware-accelerated real-time IP flow measurement method for multi-core architecture was proposed. IP datagrams were captured at wire speed of OC-192 links by FPGA. Data records were load balanced to the corresponding core-affinitive buffer queues to each processor core at flow level. Multi-stage hash values were used to detect collision when updating the flow table. Experiments show that this method can accelerate IP flow analysis effectively. With the input of 75 bytes packets, the system is able to process at wire speed of OC-192 links. This is of great significance to the online traffic identification and analysis of high speed backbones with large number of concurrent flows. |
| format | Article |
| id | doaj-art-3fff9212c360438cab5353ae3fc72607 |
| institution | OA Journals |
| issn | 1000-436X |
| language | zho |
| publishDate | 2008-01-01 |
| publisher | Editorial Department of Journal on Communications |
| record_format | Article |
| series | Tongxin xuebao |
| spelling | doaj-art-3fff9212c360438cab5353ae3fc726072025-08-20T02:09:04ZzhoEditorial Department of Journal on CommunicationsTongxin xuebao1000-436X2008-01-01291974652934Hardware-accelerated real-time IP flow measurement method for multi-core architectureZHU Chao1XIE Ying-ke1WANG Jian-dong1ZHAO Zi-li1HAN Cheng-de1A hardware-accelerated real-time IP flow measurement method for multi-core architecture was proposed. IP datagrams were captured at wire speed of OC-192 links by FPGA. Data records were load balanced to the corresponding core-affinitive buffer queues to each processor core at flow level. Multi-stage hash values were used to detect collision when updating the flow table. Experiments show that this method can accelerate IP flow analysis effectively. With the input of 75 bytes packets, the system is able to process at wire speed of OC-192 links. This is of great significance to the online traffic identification and analysis of high speed backbones with large number of concurrent flows.http://www.joconline.com.cn/thesisDetails?columnId=74652934&Fpath=home&index=0computer architecture;network measurement;hardware acceleration;IP flow;multi-core architecture;FPGA |
| spellingShingle | ZHU Chao1 XIE Ying-ke1 WANG Jian-dong1 ZHAO Zi-li1 HAN Cheng-de1 Hardware-accelerated real-time IP flow measurement method for multi-core architecture Tongxin xuebao computer architecture;network measurement;hardware acceleration;IP flow;multi-core architecture;FPGA |
| title | Hardware-accelerated real-time IP flow measurement method for multi-core architecture |
| title_full | Hardware-accelerated real-time IP flow measurement method for multi-core architecture |
| title_fullStr | Hardware-accelerated real-time IP flow measurement method for multi-core architecture |
| title_full_unstemmed | Hardware-accelerated real-time IP flow measurement method for multi-core architecture |
| title_short | Hardware-accelerated real-time IP flow measurement method for multi-core architecture |
| title_sort | hardware accelerated real time ip flow measurement method for multi core architecture |
| topic | computer architecture;network measurement;hardware acceleration;IP flow;multi-core architecture;FPGA |
| url | http://www.joconline.com.cn/thesisDetails?columnId=74652934&Fpath=home&index=0 |
| work_keys_str_mv | AT zhuchao1 hardwareacceleratedrealtimeipflowmeasurementmethodformulticorearchitecture AT xieyingke1 hardwareacceleratedrealtimeipflowmeasurementmethodformulticorearchitecture AT wangjiandong1 hardwareacceleratedrealtimeipflowmeasurementmethodformulticorearchitecture AT zhaozili1 hardwareacceleratedrealtimeipflowmeasurementmethodformulticorearchitecture AT hanchengde1 hardwareacceleratedrealtimeipflowmeasurementmethodformulticorearchitecture |