Hardware-accelerated real-time IP flow measurement method for multi-core architecture
A hardware-accelerated real-time IP flow measurement method for multi-core architecture was proposed. IP datagrams were captured at wire speed of OC-192 links by FPGA. Data records were load balanced to the corresponding core-affinitive buffer queues to each processor core at flow level. Multi-stage...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
Editorial Department of Journal on Communications
2008-01-01
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| Series: | Tongxin xuebao |
| Subjects: | |
| Online Access: | http://www.joconline.com.cn/thesisDetails?columnId=74652934&Fpath=home&index=0 |
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