Gate Engineering Effect in Ferroelectric Field‐Effect Transistors with Al‐Doped HfO2 Thin Film and Amorphous Indium‐Gallium‐Zinc‐Oxide Channel
Abstract This work investigates the mechanism for the memory window (MW) suppression of the ferroelectric‐thin film transistors (FETFTs) with an amorphous indium‐gallium‐zinc (a‐IGZO) channel. a‐IGZO generally has an n‐type character with a high bandgap (>3 eV) and a high density of gap states, h...
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Wiley-VCH
2025-03-01
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| Series: | Advanced Electronic Materials |
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| Online Access: | https://doi.org/10.1002/aelm.202400516 |
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| author | Jae Hoon Lee Yonghee Lee Joon‐Kyu Han Kyung Do Kim Seung Ryong Byun Hyeon Woo Park Cheol Seong Hwang |
| author_facet | Jae Hoon Lee Yonghee Lee Joon‐Kyu Han Kyung Do Kim Seung Ryong Byun Hyeon Woo Park Cheol Seong Hwang |
| author_sort | Jae Hoon Lee |
| collection | DOAJ |
| description | Abstract This work investigates the mechanism for the memory window (MW) suppression of the ferroelectric‐thin film transistors (FETFTs) with an amorphous indium‐gallium‐zinc (a‐IGZO) channel. a‐IGZO generally has an n‐type character with a high bandgap (>3 eV) and a high density of gap states, hindering the carrier type inversion. Therefore, the negative ferroelectric (FE) bound charges at the FE layer/a‐IGZO interface must be compensated by the positive charges of the oxygen vacancy in the a‐IGZO layer. In contrast, accumulated electrons can compensate for the positive FE‐bound charges. Such a bound charge compensation mechanism complicates the FETFT operation and precise understanding. Experiments and simulations confirm that feasible FE switching in the bottom‐TiN or P++‐Si/Al‐doped HfO2/a‐IGZO/top‐TiN structure can occur only when the countercharges in the a‐IGZO layer compensate the positive and negative bound charges. More importantly, the Al‐doped HfO2/a‐IGZO interface generally involves electron trapping, which hinders FE switching and achieving a MW for the TiN gate case. When replacing the TiN gate with the P++‐Si gate, the suppressed FE polarization by the depolarization effect from the SiO2 interface layer can mitigate electron accumulation. Consequently, the P++‐Si bottom electrode (BE) is more advantageous than the TiN BE regarding a MW of FETFT. |
| format | Article |
| id | doaj-art-3ebf60d822364c2f924cf0f586ac0e63 |
| institution | OA Journals |
| issn | 2199-160X |
| language | English |
| publishDate | 2025-03-01 |
| publisher | Wiley-VCH |
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| series | Advanced Electronic Materials |
| spelling | doaj-art-3ebf60d822364c2f924cf0f586ac0e632025-08-20T01:58:04ZengWiley-VCHAdvanced Electronic Materials2199-160X2025-03-01113n/an/a10.1002/aelm.202400516Gate Engineering Effect in Ferroelectric Field‐Effect Transistors with Al‐Doped HfO2 Thin Film and Amorphous Indium‐Gallium‐Zinc‐Oxide ChannelJae Hoon Lee0Yonghee Lee1Joon‐Kyu Han2Kyung Do Kim3Seung Ryong Byun4Hyeon Woo Park5Cheol Seong Hwang6Department of Materials Science and Engineering and Inter‐University Semiconductor Research Center College of Engineering Seoul National University Seoul 08826 Republic of KoreaDepartment of Materials Science and Engineering and Inter‐University Semiconductor Research Center College of Engineering Seoul National University Seoul 08826 Republic of KoreaSystem Semiconductor Engineering and Department of Electronic Engineering Sogang University 35 Baekbeom‐ro, Mapo‐gu Seoul 04107 Republic of KoreaDepartment of Materials Science and Engineering and Inter‐University Semiconductor Research Center College of Engineering Seoul National University Seoul 08826 Republic of KoreaDepartment of Materials Science and Engineering and Inter‐University Semiconductor Research Center College of Engineering Seoul National University Seoul 08826 Republic of KoreaDepartment of Materials Science and Engineering and Inter‐University Semiconductor Research Center College of Engineering Seoul National University Seoul 08826 Republic of KoreaDepartment of Materials Science and Engineering and Inter‐University Semiconductor Research Center College of Engineering Seoul National University Seoul 08826 Republic of KoreaAbstract This work investigates the mechanism for the memory window (MW) suppression of the ferroelectric‐thin film transistors (FETFTs) with an amorphous indium‐gallium‐zinc (a‐IGZO) channel. a‐IGZO generally has an n‐type character with a high bandgap (>3 eV) and a high density of gap states, hindering the carrier type inversion. Therefore, the negative ferroelectric (FE) bound charges at the FE layer/a‐IGZO interface must be compensated by the positive charges of the oxygen vacancy in the a‐IGZO layer. In contrast, accumulated electrons can compensate for the positive FE‐bound charges. Such a bound charge compensation mechanism complicates the FETFT operation and precise understanding. Experiments and simulations confirm that feasible FE switching in the bottom‐TiN or P++‐Si/Al‐doped HfO2/a‐IGZO/top‐TiN structure can occur only when the countercharges in the a‐IGZO layer compensate the positive and negative bound charges. More importantly, the Al‐doped HfO2/a‐IGZO interface generally involves electron trapping, which hinders FE switching and achieving a MW for the TiN gate case. When replacing the TiN gate with the P++‐Si gate, the suppressed FE polarization by the depolarization effect from the SiO2 interface layer can mitigate electron accumulation. Consequently, the P++‐Si bottom electrode (BE) is more advantageous than the TiN BE regarding a MW of FETFT.https://doi.org/10.1002/aelm.202400516Al‐doped HfO2amorphous IGZOcharge trappingferroelectric filmsgate materialmemory window |
| spellingShingle | Jae Hoon Lee Yonghee Lee Joon‐Kyu Han Kyung Do Kim Seung Ryong Byun Hyeon Woo Park Cheol Seong Hwang Gate Engineering Effect in Ferroelectric Field‐Effect Transistors with Al‐Doped HfO2 Thin Film and Amorphous Indium‐Gallium‐Zinc‐Oxide Channel Advanced Electronic Materials Al‐doped HfO2 amorphous IGZO charge trapping ferroelectric films gate material memory window |
| title | Gate Engineering Effect in Ferroelectric Field‐Effect Transistors with Al‐Doped HfO2 Thin Film and Amorphous Indium‐Gallium‐Zinc‐Oxide Channel |
| title_full | Gate Engineering Effect in Ferroelectric Field‐Effect Transistors with Al‐Doped HfO2 Thin Film and Amorphous Indium‐Gallium‐Zinc‐Oxide Channel |
| title_fullStr | Gate Engineering Effect in Ferroelectric Field‐Effect Transistors with Al‐Doped HfO2 Thin Film and Amorphous Indium‐Gallium‐Zinc‐Oxide Channel |
| title_full_unstemmed | Gate Engineering Effect in Ferroelectric Field‐Effect Transistors with Al‐Doped HfO2 Thin Film and Amorphous Indium‐Gallium‐Zinc‐Oxide Channel |
| title_short | Gate Engineering Effect in Ferroelectric Field‐Effect Transistors with Al‐Doped HfO2 Thin Film and Amorphous Indium‐Gallium‐Zinc‐Oxide Channel |
| title_sort | gate engineering effect in ferroelectric field effect transistors with al doped hfo2 thin film and amorphous indium gallium zinc oxide channel |
| topic | Al‐doped HfO2 amorphous IGZO charge trapping ferroelectric films gate material memory window |
| url | https://doi.org/10.1002/aelm.202400516 |
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