Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access Speed
A novel Asymmetrical FET (AsyFET) is proposed to enhance the retention of gain cell memory and is experimentally demonstrated based on standard 300mm logic foundry platform. In AsyFET, the asymmetrical S/D doping and S/D gate spacer are designed to suppress leakage current. The modulated Schottky di...
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2025-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10879406/ |
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| author | Kaifeng Wang Pengfei Hao Fangxing Zhang Lining Zhang Qianqian Huang Ru Huang |
| author_facet | Kaifeng Wang Pengfei Hao Fangxing Zhang Lining Zhang Qianqian Huang Ru Huang |
| author_sort | Kaifeng Wang |
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| description | A novel Asymmetrical FET (AsyFET) is proposed to enhance the retention of gain cell memory and is experimentally demonstrated based on standard 300mm logic foundry platform. In AsyFET, the asymmetrical S/D doping and S/D gate spacer are designed to suppress leakage current. The modulated Schottky direct tunneling current and band-to-band tunneling current are designed to write “1” and “0” respectively without write disturb. The AsyFET-based 2T0C DRAM with significantly enhanced retention and fast access speed is also proposed and experimentally demonstrated on the same wafer. Without area penalty or new materials, the fabricated Si AsyFET can obtain ultralow off-state current of <inline-formula> <tex-math notation="LaTeX">$\sim 10{^{-}17 }$ </tex-math></inline-formula>A/<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m, leading to the long retention above second-level in 55nm technology node across the 300mm wafer. The on-state currents of AsyFET at forward and reverse bias are <inline-formula> <tex-math notation="LaTeX">$\sim 10{^{-}6 }$ </tex-math></inline-formula>A/<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m, enabling write speed of below 5ns with negligible temperature dependence. The experimental results show the great potential of proposed AsyFET 2T0C DRAM design for low-power, high-density, and high-speed on-chip memory. |
| format | Article |
| id | doaj-art-3dea44850e124d029637c20760a4331f |
| institution | Kabale University |
| issn | 2168-6734 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-3dea44850e124d029637c20760a4331f2025-08-20T03:40:26ZengIEEEIEEE Journal of the Electron Devices Society2168-67342025-01-011323724410.1109/JEDS.2025.354058110879406Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access SpeedKaifeng Wang0https://orcid.org/0009-0007-3331-7716Pengfei Hao1Fangxing Zhang2Lining Zhang3https://orcid.org/0000-0003-1472-7852Qianqian Huang4https://orcid.org/0000-0002-3714-8581Ru Huang5School of Integrated Circuits, Peking University, Beijing, ChinaSchool of Integrated Circuits, Peking University, Beijing, ChinaSchool of Electronic and Computer Engineering, Peking University, Shenzhen, ChinaSchool of Electronic and Computer Engineering, Peking University, Shenzhen, ChinaSchool of Integrated Circuits, Peking University, Beijing, ChinaSchool of Integrated Circuits, Peking University, Beijing, ChinaA novel Asymmetrical FET (AsyFET) is proposed to enhance the retention of gain cell memory and is experimentally demonstrated based on standard 300mm logic foundry platform. In AsyFET, the asymmetrical S/D doping and S/D gate spacer are designed to suppress leakage current. The modulated Schottky direct tunneling current and band-to-band tunneling current are designed to write “1” and “0” respectively without write disturb. The AsyFET-based 2T0C DRAM with significantly enhanced retention and fast access speed is also proposed and experimentally demonstrated on the same wafer. Without area penalty or new materials, the fabricated Si AsyFET can obtain ultralow off-state current of <inline-formula> <tex-math notation="LaTeX">$\sim 10{^{-}17 }$ </tex-math></inline-formula>A/<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m, leading to the long retention above second-level in 55nm technology node across the 300mm wafer. The on-state currents of AsyFET at forward and reverse bias are <inline-formula> <tex-math notation="LaTeX">$\sim 10{^{-}6 }$ </tex-math></inline-formula>A/<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m, enabling write speed of below 5ns with negligible temperature dependence. The experimental results show the great potential of proposed AsyFET 2T0C DRAM design for low-power, high-density, and high-speed on-chip memory.https://ieeexplore.ieee.org/document/10879406/AsyFETeDRAMgain cell2T0CTFET |
| spellingShingle | Kaifeng Wang Pengfei Hao Fangxing Zhang Lining Zhang Qianqian Huang Ru Huang Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access Speed IEEE Journal of the Electron Devices Society AsyFET eDRAM gain cell 2T0C TFET |
| title | Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access Speed |
| title_full | Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access Speed |
| title_fullStr | Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access Speed |
| title_full_unstemmed | Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access Speed |
| title_short | Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access Speed |
| title_sort | logic compatible asymmetrical fet for gain cell edram with long retention and fast access speed |
| topic | AsyFET eDRAM gain cell 2T0C TFET |
| url | https://ieeexplore.ieee.org/document/10879406/ |
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