Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access Speed
A novel Asymmetrical FET (AsyFET) is proposed to enhance the retention of gain cell memory and is experimentally demonstrated based on standard 300mm logic foundry platform. In AsyFET, the asymmetrical S/D doping and S/D gate spacer are designed to suppress leakage current. The modulated Schottky di...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10879406/ |
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