A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit
Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design sch...
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| Format: | Article |
| Language: | English |
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Wiley
2023-01-01
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| Series: | IET Circuits, Devices and Systems |
| Online Access: | http://dx.doi.org/10.1049/2023/1548352 |
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| author | Wanlong Zhao Yuejun Zhang Liang Wen Pengjun Wang |
| author_facet | Wanlong Zhao Yuejun Zhang Liang Wen Pengjun Wang |
| author_sort | Wanlong Zhao |
| collection | DOAJ |
| description | Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design scheme. First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of the read/write process by clock double edges to solve multiport read/write conflicts, designed a mirror memory check circuit to avoid write errors caused by the word line delays, and used a phase-locked clock feedback structure to eliminate read errors caused by the data timing fluctuations; in the TSMC 7 nm FinFET process, a 64 × 74-bit 5R4W Regfile circuit was implemented using a fully customized layout. Experimental results show that the Regfile circuit has an area of 0.13 mm2 and consumes 5.541 mW. The circuit operates at a maximum frequency of 3.8 GHz at −40 to −125°C and 0.75 V, and is capable of detecting write errors caused by a clock jitter exceeding 30 ps or a frequency above 5 GHz. |
| format | Article |
| id | doaj-art-3548847077864f0ea58067535c6a6055 |
| institution | Kabale University |
| issn | 1751-8598 |
| language | English |
| publishDate | 2023-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-3548847077864f0ea58067535c6a60552025-02-03T01:29:34ZengWileyIET Circuits, Devices and Systems1751-85982023-01-01202310.1049/2023/1548352A 7-nm-Based 5R4W High-Timing Reliability Regfile CircuitWanlong Zhao0Yuejun Zhang1Liang Wen2Pengjun Wang3Faculty of Electrical Engineering and Computer ScienceFaculty of Electrical Engineering and Computer ScienceDepartment of Electronic TechnologyCollege of Electrical and Electronic EngineeringRegister file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design scheme. First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of the read/write process by clock double edges to solve multiport read/write conflicts, designed a mirror memory check circuit to avoid write errors caused by the word line delays, and used a phase-locked clock feedback structure to eliminate read errors caused by the data timing fluctuations; in the TSMC 7 nm FinFET process, a 64 × 74-bit 5R4W Regfile circuit was implemented using a fully customized layout. Experimental results show that the Regfile circuit has an area of 0.13 mm2 and consumes 5.541 mW. The circuit operates at a maximum frequency of 3.8 GHz at −40 to −125°C and 0.75 V, and is capable of detecting write errors caused by a clock jitter exceeding 30 ps or a frequency above 5 GHz.http://dx.doi.org/10.1049/2023/1548352 |
| spellingShingle | Wanlong Zhao Yuejun Zhang Liang Wen Pengjun Wang A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit IET Circuits, Devices and Systems |
| title | A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit |
| title_full | A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit |
| title_fullStr | A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit |
| title_full_unstemmed | A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit |
| title_short | A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit |
| title_sort | 7 nm based 5r4w high timing reliability regfile circuit |
| url | http://dx.doi.org/10.1049/2023/1548352 |
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