A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit
Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design sch...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2023-01-01
|
| Series: | IET Circuits, Devices and Systems |
| Online Access: | http://dx.doi.org/10.1049/2023/1548352 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|