A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application
Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single e...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2018-01-01
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| Series: | Journal of Nanotechnology |
| Online Access: | http://dx.doi.org/10.1155/2018/2934268 |
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