Scaling Logic Area With Multitier Standard Cells
While the footprint of digital complementary metal-oxide–semiconductor (CMOS) circuits has continued to decrease over the years, physical limitations for further intralayer geometric scaling become apparent. To further increase the logic density, the international roadmap for devices and...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
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| Online Access: | https://ieeexplore.ieee.org/document/10720813/ |
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| _version_ | 1841526334130487296 |
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| author | Florian Freye Christian Lanius Hossein Hashemi Shadmehri Diana Gohringer Tobias Gemmeke |
| author_facet | Florian Freye Christian Lanius Hossein Hashemi Shadmehri Diana Gohringer Tobias Gemmeke |
| author_sort | Florian Freye |
| collection | DOAJ |
| description | While the footprint of digital complementary metal-oxide–semiconductor (CMOS) circuits has continued to decrease over the years, physical limitations for further intralayer geometric scaling become apparent. To further increase the logic density, the international roadmap for devices and systems (IRDS) predicts a transition from a single layer of transistors per die to monolithically stacking transistors in multiple tiers starting in 2031. This raises the question of the extent to which these can be exploited in 3-D standard cells to improve logic density. In this work, we investigate the scaling potential of realizing standard cells employing two or three dedicated tiers. For this, specific multitier virtual physical design kits are derived based on the open ASAP7. A typical RISC-V implementation realized in a classic standard cell library is used to identify the subset of the most relevant standard cells. In accordance with the virtual physical design kit (PDK), 3-D derivatives of the single-tier standard cells are crafted and evaluated with respect to achievable logic density considering standard synthesis benchmarks and blocks on the architecture level. |
| format | Article |
| id | doaj-art-2b5202b71b054a29831fd711af4f3481 |
| institution | Kabale University |
| issn | 2329-9231 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj-art-2b5202b71b054a29831fd711af4f34812025-01-17T00:00:37ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312024-01-0110828810.1109/JXCDC.2024.348246410720813Scaling Logic Area With Multitier Standard CellsFlorian Freye0https://orcid.org/0000-0003-3025-8910Christian Lanius1https://orcid.org/0000-0001-7107-3782Hossein Hashemi Shadmehri2https://orcid.org/0000-0002-5447-8451Diana Gohringer3https://orcid.org/0000-0003-2571-8441Tobias Gemmeke4https://orcid.org/0000-0003-1583-3411Chair of Integrated Digital Systems and Circuit Design, Aachen, GermanyChair of Integrated Digital Systems and Circuit Design, Aachen, GermanyChair of Integrated Digital Systems and Circuit Design, Aachen, GermanyChair of Adaptive Dynamic Systems, Dresden, GermanyChair of Integrated Digital Systems and Circuit Design, Aachen, GermanyWhile the footprint of digital complementary metal-oxide–semiconductor (CMOS) circuits has continued to decrease over the years, physical limitations for further intralayer geometric scaling become apparent. To further increase the logic density, the international roadmap for devices and systems (IRDS) predicts a transition from a single layer of transistors per die to monolithically stacking transistors in multiple tiers starting in 2031. This raises the question of the extent to which these can be exploited in 3-D standard cells to improve logic density. In this work, we investigate the scaling potential of realizing standard cells employing two or three dedicated tiers. For this, specific multitier virtual physical design kits are derived based on the open ASAP7. A typical RISC-V implementation realized in a classic standard cell library is used to identify the subset of the most relevant standard cells. In accordance with the virtual physical design kit (PDK), 3-D derivatives of the single-tier standard cells are crafted and evaluated with respect to achievable logic density considering standard synthesis benchmarks and blocks on the architecture level.https://ieeexplore.ieee.org/document/10720813/Advanced scalingmonolithic 3-D integrationmultitier circuitsstandard cell library |
| spellingShingle | Florian Freye Christian Lanius Hossein Hashemi Shadmehri Diana Gohringer Tobias Gemmeke Scaling Logic Area With Multitier Standard Cells IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Advanced scaling monolithic 3-D integration multitier circuits standard cell library |
| title | Scaling Logic Area With Multitier Standard Cells |
| title_full | Scaling Logic Area With Multitier Standard Cells |
| title_fullStr | Scaling Logic Area With Multitier Standard Cells |
| title_full_unstemmed | Scaling Logic Area With Multitier Standard Cells |
| title_short | Scaling Logic Area With Multitier Standard Cells |
| title_sort | scaling logic area with multitier standard cells |
| topic | Advanced scaling monolithic 3-D integration multitier circuits standard cell library |
| url | https://ieeexplore.ieee.org/document/10720813/ |
| work_keys_str_mv | AT florianfreye scalinglogicareawithmultitierstandardcells AT christianlanius scalinglogicareawithmultitierstandardcells AT hosseinhashemishadmehri scalinglogicareawithmultitierstandardcells AT dianagohringer scalinglogicareawithmultitierstandardcells AT tobiasgemmeke scalinglogicareawithmultitierstandardcells |