Memory State Dynamics in BEOL FeFETs: Impact of Area Ratio on Analog Write Mechanisms and Charging
This work presents dynamic state writing by combining ferroelectric (FE) polarization together with charge injection (CI) on Si-based ferroelectric MOSFETs as a novel approach for non-volatile memory design. FE capacitors are non-destructively integrated in the Back-End-of-Line (BEOL) with Si MOSFET...
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| Format: | Article |
| Language: | English |
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10835082/ |
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| author | Hannes Dahlberg Oscar Kaatranen Karl-Magnus Persson Arto Rantala Jacek Flak Lars-Erik Wernersson |
| author_facet | Hannes Dahlberg Oscar Kaatranen Karl-Magnus Persson Arto Rantala Jacek Flak Lars-Erik Wernersson |
| author_sort | Hannes Dahlberg |
| collection | DOAJ |
| description | This work presents dynamic state writing by combining ferroelectric (FE) polarization together with charge injection (CI) on Si-based ferroelectric MOSFETs as a novel approach for non-volatile memory design. FE capacitors are non-destructively integrated in the Back-End-of-Line (BEOL) with Si MOSFETs to create FE-Metal-FETs (FeMFETs). We explore the FE/MOS area ratio (AR) as a critical design parameter, particularly in the context of dynamic writing processes, where various voltage pulse trains are applied for analog potentiation and depression of the memory state. AR significantly influences both the electric field distribution over the FE and the extent of CI from the top electrode. Constant-pulse writing schemes enable analog threshold voltage modulation by considering the AR, with reduced voltages and faster operation for smaller ARs. Retention of intermittent states written by FE polarization combined with CI is demonstrated, illustrating the stability and effectiveness of FeMFET devices and AR optimization for memory applications. |
| format | Article |
| id | doaj-art-2b10b6b1941f491296d8e86043e47e41 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-2b10b6b1941f491296d8e86043e47e412025-01-21T00:02:07ZengIEEEIEEE Access2169-35362025-01-01139923993010.1109/ACCESS.2025.352762810835082Memory State Dynamics in BEOL FeFETs: Impact of Area Ratio on Analog Write Mechanisms and ChargingHannes Dahlberg0https://orcid.org/0000-0002-6787-3346Oscar Kaatranen1Karl-Magnus Persson2Arto Rantala3https://orcid.org/0000-0002-8075-0113Jacek Flak4https://orcid.org/0000-0002-2943-3788Lars-Erik Wernersson5https://orcid.org/0000-0002-1039-5849Department of Electrical and Information Technology, Division of Electromagnetics and Nanoelectronics, Lund University, Lund, SwedenVTT Technical Research Centre of Finland Ltd., Espoo, FinlandVTT Technical Research Centre of Finland Ltd., Espoo, FinlandVTT Technical Research Centre of Finland Ltd., Espoo, FinlandVTT Technical Research Centre of Finland Ltd., Espoo, FinlandDepartment of Electrical and Information Technology, Division of Electromagnetics and Nanoelectronics, Lund University, Lund, SwedenThis work presents dynamic state writing by combining ferroelectric (FE) polarization together with charge injection (CI) on Si-based ferroelectric MOSFETs as a novel approach for non-volatile memory design. FE capacitors are non-destructively integrated in the Back-End-of-Line (BEOL) with Si MOSFETs to create FE-Metal-FETs (FeMFETs). We explore the FE/MOS area ratio (AR) as a critical design parameter, particularly in the context of dynamic writing processes, where various voltage pulse trains are applied for analog potentiation and depression of the memory state. AR significantly influences both the electric field distribution over the FE and the extent of CI from the top electrode. Constant-pulse writing schemes enable analog threshold voltage modulation by considering the AR, with reduced voltages and faster operation for smaller ARs. Retention of intermittent states written by FE polarization combined with CI is demonstrated, illustrating the stability and effectiveness of FeMFET devices and AR optimization for memory applications.https://ieeexplore.ieee.org/document/10835082/BEOL integrationCMOSFeFETferroelectricityHZOnon-volatile memory |
| spellingShingle | Hannes Dahlberg Oscar Kaatranen Karl-Magnus Persson Arto Rantala Jacek Flak Lars-Erik Wernersson Memory State Dynamics in BEOL FeFETs: Impact of Area Ratio on Analog Write Mechanisms and Charging IEEE Access BEOL integration CMOS FeFET ferroelectricity HZO non-volatile memory |
| title | Memory State Dynamics in BEOL FeFETs: Impact of Area Ratio on Analog Write Mechanisms and Charging |
| title_full | Memory State Dynamics in BEOL FeFETs: Impact of Area Ratio on Analog Write Mechanisms and Charging |
| title_fullStr | Memory State Dynamics in BEOL FeFETs: Impact of Area Ratio on Analog Write Mechanisms and Charging |
| title_full_unstemmed | Memory State Dynamics in BEOL FeFETs: Impact of Area Ratio on Analog Write Mechanisms and Charging |
| title_short | Memory State Dynamics in BEOL FeFETs: Impact of Area Ratio on Analog Write Mechanisms and Charging |
| title_sort | memory state dynamics in beol fefets impact of area ratio on analog write mechanisms and charging |
| topic | BEOL integration CMOS FeFET ferroelectricity HZO non-volatile memory |
| url | https://ieeexplore.ieee.org/document/10835082/ |
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