IGZO 2T0C DRAM With V<sub>TH</sub> Compensation Technique for Multi-Bit Applications
In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-ce...
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IEEE
2025-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10979978/ |
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| author | Kaifei Chen Wendong Lu Jiebin Niu Menggan Liu Fuxi Liao Xuanming Zhang Zihan Li Naide Mao Kaiping Zhang Congyan Lu Bok-Moon Kang Jiawei Wang Di Geng Nianduan Lu Guilei Wang Zhengyong Zhu Guanhua Yang Chao Zhao Arokia Nathan Ling Li Ming Liu |
| author_facet | Kaifei Chen Wendong Lu Jiebin Niu Menggan Liu Fuxi Liao Xuanming Zhang Zihan Li Naide Mao Kaiping Zhang Congyan Lu Bok-Moon Kang Jiawei Wang Di Geng Nianduan Lu Guilei Wang Zhengyong Zhu Guanhua Yang Chao Zhao Arokia Nathan Ling Li Ming Liu |
| author_sort | Kaifei Chen |
| collection | DOAJ |
| description | In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-cell is discharging process from storage node (SN) to bit line, achieving in-cell threshold voltage (VTH) compensation without sacrificing bit-cell layout. VTH modulation derived from the top gate of read transistor makes noticeable <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VSN boosting, with a record-high ratio (<inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VSN/<inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VDATA) of 1.46, which improves the headroom for multi-bit storage. Moreover, the optimized transistors with positive VTH and high ON-state current enable long retention time (>1500 s) and ultra-fast writing speed (< 10 ns). Under the synergistic effect of VTH compensation and <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VSN boosting, non-overlap 3-bit storage operation among 25 cells is achieved with one order reduction of standard deviation. This study establishes a critical foundation for implementing multi-bit storage applications of IGZO 2T0C DRAM in large-scale array. |
| format | Article |
| id | doaj-art-299e505ee7ef43498e057314c7f58ecb |
| institution | OA Journals |
| issn | 2168-6734 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-299e505ee7ef43498e057314c7f58ecb2025-08-20T02:32:16ZengIEEEIEEE Journal of the Electron Devices Society2168-67342025-01-011343944310.1109/JEDS.2025.356565810979978IGZO 2T0C DRAM With V<sub>TH</sub> Compensation Technique for Multi-Bit ApplicationsKaifei Chen0https://orcid.org/0009-0008-1317-8015Wendong Lu1Jiebin Niu2https://orcid.org/0009-0009-6299-0947Menggan Liu3Fuxi Liao4https://orcid.org/0009-0008-1441-0947Xuanming Zhang5Zihan Li6Naide Mao7Kaiping Zhang8Congyan Lu9Bok-Moon Kang10Jiawei Wang11https://orcid.org/0000-0002-3043-8447Di Geng12https://orcid.org/0000-0002-5653-6811Nianduan Lu13https://orcid.org/0000-0001-8415-7627Guilei Wang14https://orcid.org/0000-0002-1311-8863Zhengyong Zhu15Guanhua Yang16https://orcid.org/0000-0003-4694-7040Chao Zhao17https://orcid.org/0009-0009-2026-2714Arokia Nathan18https://orcid.org/0000-0002-2070-8853Ling Li19https://orcid.org/0000-0002-7622-8752Ming Liu20https://orcid.org/0000-0002-0937-7547Key Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaBejing Superstring Academy of Memory Technology, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaBejing Superstring Academy of Memory Technology, Beijing, ChinaBejing Superstring Academy of Memory Technology, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaBejing Superstring Academy of Memory Technology, Beijing, ChinaDarwin College, Cambridge University, Cambridge, U.K.Key Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaIn this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-cell is discharging process from storage node (SN) to bit line, achieving in-cell threshold voltage (VTH) compensation without sacrificing bit-cell layout. VTH modulation derived from the top gate of read transistor makes noticeable <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VSN boosting, with a record-high ratio (<inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VSN/<inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VDATA) of 1.46, which improves the headroom for multi-bit storage. Moreover, the optimized transistors with positive VTH and high ON-state current enable long retention time (>1500 s) and ultra-fast writing speed (< 10 ns). Under the synergistic effect of VTH compensation and <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VSN boosting, non-overlap 3-bit storage operation among 25 cells is achieved with one order reduction of standard deviation. This study establishes a critical foundation for implementing multi-bit storage applications of IGZO 2T0C DRAM in large-scale array.https://ieeexplore.ieee.org/document/10979978/Multi-bitarray leveldual gate2T0C DRAMIGZOVTH compensation |
| spellingShingle | Kaifei Chen Wendong Lu Jiebin Niu Menggan Liu Fuxi Liao Xuanming Zhang Zihan Li Naide Mao Kaiping Zhang Congyan Lu Bok-Moon Kang Jiawei Wang Di Geng Nianduan Lu Guilei Wang Zhengyong Zhu Guanhua Yang Chao Zhao Arokia Nathan Ling Li Ming Liu IGZO 2T0C DRAM With V<sub>TH</sub> Compensation Technique for Multi-Bit Applications IEEE Journal of the Electron Devices Society Multi-bit array level dual gate 2T0C DRAM IGZO VTH compensation |
| title | IGZO 2T0C DRAM With V<sub>TH</sub> Compensation Technique for Multi-Bit Applications |
| title_full | IGZO 2T0C DRAM With V<sub>TH</sub> Compensation Technique for Multi-Bit Applications |
| title_fullStr | IGZO 2T0C DRAM With V<sub>TH</sub> Compensation Technique for Multi-Bit Applications |
| title_full_unstemmed | IGZO 2T0C DRAM With V<sub>TH</sub> Compensation Technique for Multi-Bit Applications |
| title_short | IGZO 2T0C DRAM With V<sub>TH</sub> Compensation Technique for Multi-Bit Applications |
| title_sort | igzo 2t0c dram with v sub th sub compensation technique for multi bit applications |
| topic | Multi-bit array level dual gate 2T0C DRAM IGZO VTH compensation |
| url | https://ieeexplore.ieee.org/document/10979978/ |
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