IGZO 2T0C DRAM With V<sub>TH</sub> Compensation Technique for Multi-Bit Applications

IGZO 2T0C DRAM With V<sub>TH</sub> Compensation Technique for Multi-Bit Applications

In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-ce...

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Main Authors: Kaifei Chen, Wendong Lu, Jiebin Niu, Menggan Liu, Fuxi Liao, Xuanming Zhang, Zihan Li, Naide Mao, Kaiping Zhang, Congyan Lu, Bok-Moon Kang, Jiawei Wang, Di Geng, Nianduan Lu, Guilei Wang, Zhengyong Zhu, Guanhua Yang, Chao Zhao, Arokia Nathan, Ling Li, Ming Liu
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Multi-bit
array level
dual gate
2T0C DRAM
IGZO
VTH compensation
Online Access:https://ieeexplore.ieee.org/document/10979978/
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Summary:In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-cell is discharging process from storage node (SN) to bit line, achieving in-cell threshold voltage (VTH) compensation without sacrificing bit-cell layout. VTH modulation derived from the top gate of read transistor makes noticeable <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VSN boosting, with a record-high ratio (<inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VSN/<inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VDATA) of 1.46, which improves the headroom for multi-bit storage. Moreover, the optimized transistors with positive VTH and high ON-state current enable long retention time (&#x003E;1500 s) and ultra-fast writing speed (&#x003C; 10 ns). Under the synergistic effect of VTH compensation and <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VSN boosting, non-overlap 3-bit storage operation among 25 cells is achieved with one order reduction of standard deviation. This study establishes a critical foundation for implementing multi-bit storage applications of IGZO 2T0C DRAM in large-scale array.
ISSN:2168-6734

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