Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability

Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability

This work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability. Its extensible instruction set uses sequential control flow in code fragments of up to 64 RISC-like instructions, which encode control and dataflow graphs in adj...

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Bibliographic Details
Main Authors: Tobias Kaiser, Esther Gottschalk, Kai Biethahn, Friedel Gerfers
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Open Journal of Circuits and Systems
Subjects:
Computer architecture
reconfigurable architectures
microprocessor chips
energy efficiency
code generation
on-chip interconnection networks
Online Access:https://ieeexplore.ieee.org/document/10802954/
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Summary:This work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability. Its extensible instruction set uses sequential control flow in code fragments of up to 64 RISC-like instructions, which encode control and dataflow graphs in adjacency lists. Combined with dedicated, uniform processing elements, this enables fast compilation from C source code (1.4 s mean compile time). Demonstrator measurements reveal energy efficiency of up to 601 int32 MIPS/mW at 0.59V and performance of up to 148 MIPS at 0.90 V. Compared to a RISC reference system, mean energy efficiency is improved by 2.24× with 1.71× higher execution times across 12 of 14 benchmarks. Program-dependent factors underlying variations in energy efficiency are identified using dynamic program analysis. To reduce operand transfer energy, seven interconnect topologies are evaluated: a flat bus, five crossbar variants and a logarithmic network. Best results are obtained for a crossbar topology, reducing mean dynamic tile energy by 19 %. Furthermore, floating-point (FP) support is added to the instruction set and evaluated using three binary-compatible microarchitectures, presenting distinct area-performance-energy tradeoffs. The interconnect and FP microarchitecture explorations demonstrate that, unlike CGRAs utilizing low-level bitstreams, Pasithea’s instruction set hides microarchitectural details, which makes it possible to optimize hardware without severing binary compatibility.
ISSN:2644-1225

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