Ultra-Low-Power 0.35-V 0.63-nW/kHz Multi-Stacked Clock Oscillator With Adjustable Frequency and Duty-Cycling

Ultra-Low-Power 0.35-V 0.63-nW/kHz Multi-Stacked Clock Oscillator With Adjustable Frequency and Duty-Cycling

This paper presents the analysis, design, and characterization of an on-chip ultra-low-power clock oscillator for sensor nodes, implemented in 130nm BiCMOS technology. The design employs a multi-stacked inverter-based ring oscillator topology which utilizes variable RC features to tune the oscillati...

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Bibliographic Details
Main Authors: Seyyedmohsen Seyyedrezaei, Jens Wagner, Frank Ellinger
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
Clock generation
clock oscillator
duty-cycling
leakage current
low voltage
relaxation oscillator
Online Access:https://ieeexplore.ieee.org/document/10943206/
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https://ieeexplore.ieee.org/document/10943206/

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