Exploring Many-Core Design Templates for FPGAs and ASICs
We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level pa...
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| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2012-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2012/439141 |
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| _version_ | 1832566801997758464 |
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| author | Ilia Lebedev Christopher Fletcher Shaoyi Cheng James Martin Austin Doupnik Daniel Burke Mingjie Lin John Wawrzynek |
| author_facet | Ilia Lebedev Christopher Fletcher Shaoyi Cheng James Martin Austin Doupnik Daniel Burke Mingjie Lin John Wawrzynek |
| author_sort | Ilia Lebedev |
| collection | DOAJ |
| description | We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i) allows programmers to express parallelism through an API defined in a high-level programming language, (ii) supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii) reduces the effort required to repurpose the system for different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU) implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms. |
| format | Article |
| id | doaj-art-1d4d1a148c524bf3a1c58d95bda41f00 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-1d4d1a148c524bf3a1c58d95bda41f002025-02-03T01:03:11ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092012-01-01201210.1155/2012/439141439141Exploring Many-Core Design Templates for FPGAs and ASICsIlia Lebedev0Christopher Fletcher1Shaoyi Cheng2James Martin3Austin Doupnik4Daniel Burke5Mingjie Lin6John Wawrzynek7CSAIL, Massachusetts Institute of Technology, Cambridge, MA 02139, USACSAIL, Massachusetts Institute of Technology, Cambridge, MA 02139, USADepartment of EECS, University of California at Berkeley, CA 94704, USADepartment of EECS, University of California at Berkeley, CA 94704, USADepartment of EECS, University of California at Berkeley, CA 94704, USADepartment of EECS, University of California at Berkeley, CA 94704, USADepartment of EECS, University of California at Berkeley, CA 94704, USADepartment of EECS, University of California at Berkeley, CA 94704, USAWe present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i) allows programmers to express parallelism through an API defined in a high-level programming language, (ii) supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii) reduces the effort required to repurpose the system for different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU) implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms.http://dx.doi.org/10.1155/2012/439141 |
| spellingShingle | Ilia Lebedev Christopher Fletcher Shaoyi Cheng James Martin Austin Doupnik Daniel Burke Mingjie Lin John Wawrzynek Exploring Many-Core Design Templates for FPGAs and ASICs International Journal of Reconfigurable Computing |
| title | Exploring Many-Core Design Templates for FPGAs and ASICs |
| title_full | Exploring Many-Core Design Templates for FPGAs and ASICs |
| title_fullStr | Exploring Many-Core Design Templates for FPGAs and ASICs |
| title_full_unstemmed | Exploring Many-Core Design Templates for FPGAs and ASICs |
| title_short | Exploring Many-Core Design Templates for FPGAs and ASICs |
| title_sort | exploring many core design templates for fpgas and asics |
| url | http://dx.doi.org/10.1155/2012/439141 |
| work_keys_str_mv | AT ilialebedev exploringmanycoredesigntemplatesforfpgasandasics AT christopherfletcher exploringmanycoredesigntemplatesforfpgasandasics AT shaoyicheng exploringmanycoredesigntemplatesforfpgasandasics AT jamesmartin exploringmanycoredesigntemplatesforfpgasandasics AT austindoupnik exploringmanycoredesigntemplatesforfpgasandasics AT danielburke exploringmanycoredesigntemplatesforfpgasandasics AT mingjielin exploringmanycoredesigntemplatesforfpgasandasics AT johnwawrzynek exploringmanycoredesigntemplatesforfpgasandasics |