CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability
This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging effects. A rigorously calibrated TCAD model, validated against experimental CFET d...
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2025-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
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| Online Access: | https://ieeexplore.ieee.org/document/10994809/ |
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| author | Sufia Shahin Swati Deshwal Anirban Kar Mahdi Benkhelifa Yogesh S. Chauhan Hussam Amrouch |
| author_facet | Sufia Shahin Swati Deshwal Anirban Kar Mahdi Benkhelifa Yogesh S. Chauhan Hussam Amrouch |
| author_sort | Sufia Shahin |
| collection | DOAJ |
| description | This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging effects. A rigorously calibrated TCAD model, validated against experimental CFET data, is employed to quantify the impact of metal gate granularity (MGG)-induced work-function variation (WFV) and random dopant fluctuation (RDF) on key device parameters, including the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {TH}}$ </tex-math></inline-formula>), <sc>on</sc>-state current (<inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {ON}}$ </tex-math></inline-formula>), and <sc>off</sc>-state current (<inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {OFF}}$ </tex-math></inline-formula>). Temperature-dependent variability is systematically analyzed to further elucidate the behavior of these advanced devices. To capture the dynamic effects of aging, the reaction-diffusion (RD) framework—which accounts for defect generation due to negative bias temperature instability (NBTI)—is implemented in TCAD, enabling detailed modeling of trap generation and the corresponding <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {TH}}$ </tex-math></inline-formula> shifts in p-type transistors under varying gate stress biases (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {GSTR}}$ </tex-math></inline-formula>) and operating temperatures. At the circuit level, a full array of 6T-static random access memory (SRAM) cells with the requisite peripheral circuits is simulated using SPICE after careful calibration of the industry-standard compact model of gate-all-around (BSIM-CMG) against the TCAD data. The variability analysis reveals that the access disturb margin achieves a cell sigma (<inline-formula> <tex-math notation="LaTeX">$\mu /\sigma $ </tex-math></inline-formula>) of 17.4 at nominal supply voltage, significantly exceeding the <inline-formula> <tex-math notation="LaTeX">$6\sigma $ </tex-math></inline-formula> robustness criterion for read disturbances. Moreover, as the operating temperature increases from 300 to 398 K, the read static noise margin (RSNM) and hold static noise margin (HSNM) degrade by 13.7% and 6.37%, respectively, while the write static noise margin (WSNM) improves by 18.3%. These findings provide critical insights into the design tradeoffs and reliability challenges of CFET-based SRAMs. |
| format | Article |
| id | doaj-art-1d3d63cc63634053b79489433a6a9b49 |
| institution | Kabale University |
| issn | 2329-9231 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
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| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj-art-1d3d63cc63634053b79489433a6a9b492025-08-20T03:46:53ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312025-01-0111515910.1109/JXCDC.2025.356862210994809CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time VariabilitySufia Shahin0https://orcid.org/0009-0004-0134-980XSwati Deshwal1https://orcid.org/0009-0000-2084-0996Anirban Kar2https://orcid.org/0000-0003-0727-6192Mahdi Benkhelifa3https://orcid.org/0000-0002-8982-2902Yogesh S. Chauhan4https://orcid.org/0000-0002-3356-8917Hussam Amrouch5https://orcid.org/0000-0002-5649-3102TUM School of Computation, Information and Technology, Chair of AI Processor Design, Munich Institute of Robotics and Machine Intelligence, Technical University of Munich, Munich, GermanyTUM School of Computation, Information and Technology, Chair of AI Processor Design, Munich Institute of Robotics and Machine Intelligence, Technical University of Munich, Munich, GermanyTUM School of Computation, Information and Technology, Chair of AI Processor Design, Munich Institute of Robotics and Machine Intelligence, Technical University of Munich, Munich, GermanyTUM School of Computation, Information and Technology, Chair of AI Processor Design, Munich Institute of Robotics and Machine Intelligence, Technical University of Munich, Munich, GermanyDepartment of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, IndiaTUM School of Computation, Information and Technology, Chair of AI Processor Design, Munich Institute of Robotics and Machine Intelligence, Technical University of Munich, Munich, GermanyThis work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging effects. A rigorously calibrated TCAD model, validated against experimental CFET data, is employed to quantify the impact of metal gate granularity (MGG)-induced work-function variation (WFV) and random dopant fluctuation (RDF) on key device parameters, including the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {TH}}$ </tex-math></inline-formula>), <sc>on</sc>-state current (<inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {ON}}$ </tex-math></inline-formula>), and <sc>off</sc>-state current (<inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {OFF}}$ </tex-math></inline-formula>). Temperature-dependent variability is systematically analyzed to further elucidate the behavior of these advanced devices. To capture the dynamic effects of aging, the reaction-diffusion (RD) framework—which accounts for defect generation due to negative bias temperature instability (NBTI)—is implemented in TCAD, enabling detailed modeling of trap generation and the corresponding <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {TH}}$ </tex-math></inline-formula> shifts in p-type transistors under varying gate stress biases (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {GSTR}}$ </tex-math></inline-formula>) and operating temperatures. At the circuit level, a full array of 6T-static random access memory (SRAM) cells with the requisite peripheral circuits is simulated using SPICE after careful calibration of the industry-standard compact model of gate-all-around (BSIM-CMG) against the TCAD data. The variability analysis reveals that the access disturb margin achieves a cell sigma (<inline-formula> <tex-math notation="LaTeX">$\mu /\sigma $ </tex-math></inline-formula>) of 17.4 at nominal supply voltage, significantly exceeding the <inline-formula> <tex-math notation="LaTeX">$6\sigma $ </tex-math></inline-formula> robustness criterion for read disturbances. Moreover, as the operating temperature increases from 300 to 398 K, the read static noise margin (RSNM) and hold static noise margin (HSNM) degrade by 13.7% and 6.37%, respectively, while the write static noise margin (WSNM) improves by 18.3%. These findings provide critical insights into the design tradeoffs and reliability challenges of CFET-based SRAMs.https://ieeexplore.ieee.org/document/10994809/Agingcompact modelingCFETprocess variationSRAMTCAD |
| spellingShingle | Sufia Shahin Swati Deshwal Anirban Kar Mahdi Benkhelifa Yogesh S. Chauhan Hussam Amrouch CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Aging compact modeling CFET process variation SRAM TCAD |
| title | CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability |
| title_full | CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability |
| title_fullStr | CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability |
| title_full_unstemmed | CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability |
| title_short | CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability |
| title_sort | cfet beyond 3 nm sram reliability under design time and run time variability |
| topic | Aging compact modeling CFET process variation SRAM TCAD |
| url | https://ieeexplore.ieee.org/document/10994809/ |
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