Wu’s Characteristic Set Method for SystemVerilog Assertions Verification
We propose a verification solution based on characteristic set of Wu’s method towards SystemVerilog assertion checking over digital circuit systems. We define a suitable subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2013-01-01
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| Series: | Journal of Applied Mathematics |
| Online Access: | http://dx.doi.org/10.1155/2013/740194 |
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| _version_ | 1832549915712028672 |
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| author | Xinyan Gao Ning Zhou Jinzhao Wu Dakui Li |
| author_facet | Xinyan Gao Ning Zhou Jinzhao Wu Dakui Li |
| author_sort | Xinyan Gao |
| collection | DOAJ |
| description | We propose a verification solution based on characteristic set of Wu’s method towards SystemVerilog assertion checking over digital circuit systems. We define a suitable subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We present an algorithm framework based on the algebraic representations using characteristic set of polynomial system. This symbolic algebraic approach is a useful supplement to the existent verification methods based on simulation. |
| format | Article |
| id | doaj-art-1b3bd6fb20d64f92b43fdc45e83f8f4e |
| institution | Kabale University |
| issn | 1110-757X 1687-0042 |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Applied Mathematics |
| spelling | doaj-art-1b3bd6fb20d64f92b43fdc45e83f8f4e2025-02-03T06:08:14ZengWileyJournal of Applied Mathematics1110-757X1687-00422013-01-01201310.1155/2013/740194740194Wu’s Characteristic Set Method for SystemVerilog Assertions VerificationXinyan Gao0Ning Zhou1Jinzhao Wu2Dakui Li3School of Software of Dalian University of Technology, Dalian 116620, ChinaSchool of Computer and Information Technology, Beijing Jiaotong University, Beijing 10044, ChinaGuangxi Key Laboratory of Hybrid Computation and IC Design Analysis, Guangxi University for Nationalities, Nanning 530006, ChinaSchool of Software of Dalian University of Technology, Dalian 116620, ChinaWe propose a verification solution based on characteristic set of Wu’s method towards SystemVerilog assertion checking over digital circuit systems. We define a suitable subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We present an algorithm framework based on the algebraic representations using characteristic set of polynomial system. This symbolic algebraic approach is a useful supplement to the existent verification methods based on simulation.http://dx.doi.org/10.1155/2013/740194 |
| spellingShingle | Xinyan Gao Ning Zhou Jinzhao Wu Dakui Li Wu’s Characteristic Set Method for SystemVerilog Assertions Verification Journal of Applied Mathematics |
| title | Wu’s Characteristic Set Method for SystemVerilog Assertions Verification |
| title_full | Wu’s Characteristic Set Method for SystemVerilog Assertions Verification |
| title_fullStr | Wu’s Characteristic Set Method for SystemVerilog Assertions Verification |
| title_full_unstemmed | Wu’s Characteristic Set Method for SystemVerilog Assertions Verification |
| title_short | Wu’s Characteristic Set Method for SystemVerilog Assertions Verification |
| title_sort | wu s characteristic set method for systemverilog assertions verification |
| url | http://dx.doi.org/10.1155/2013/740194 |
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