Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders
In the rate-distortion optimization (RDO), the process of choosing the best prediction mode is performed through exhaustive executions of the whole encoding process, increasing significantly the encoder computational complexity. Considering H.264/AVC intra frame prediction, there are several modes t...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2012-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2012/813023 |
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| _version_ | 1832549772291997696 |
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| author | Daniel Palomino Guilherme Corrêa Cláudio Diniz Sergio Bampi Luciano Agostini Altamiro Susin |
| author_facet | Daniel Palomino Guilherme Corrêa Cláudio Diniz Sergio Bampi Luciano Agostini Altamiro Susin |
| author_sort | Daniel Palomino |
| collection | DOAJ |
| description | In the rate-distortion optimization (RDO), the process of choosing the best prediction mode is performed through exhaustive executions of the whole encoding process, increasing significantly the encoder computational complexity. Considering H.264/AVC intra frame prediction, there are several modes to encode a macroblock (MB). This work proposes an algorithm and the hardware design for a fast intra frame mode decision module for H.264/AVC encoders. The application of the proposed algorithm reduces in more than 10 times the number of encoding iterations for choosing the best intramode when compared with RDO-based decision. The architecture was synthesized to FPGA and achieved an operation frequency of 98 MHz processing more than 300 HD1080p frames per second. With this approach, we achieved one order-of-magnitude performance improvement compared with RDO-based approaches, which is very important not only from the performance but also from the energy consumption perspective for battery-operated devices. In order to compare the architecture with previously published works, we also synthesized it to standard cells. Compared with the best previous results reported, the implemented architecture achieves a complexity reduction of five times, a processing capability increase of 14 times, and a reduction in the number of clock cycles per MB of 11 times. |
| format | Article |
| id | doaj-art-18d0cf6d7fea48ec879f9e51758fe1ba |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-18d0cf6d7fea48ec879f9e51758fe1ba2025-02-03T06:08:30ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092012-01-01201210.1155/2012/813023813023Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC EncodersDaniel Palomino0Guilherme Corrêa1Cláudio Diniz2Sergio Bampi3Luciano Agostini4Altamiro Susin5Microelectronics Group, INF, Federal University of Rio Grande do Sul, Avenida Bento Gonçalves 9500, P.O. Box 15064, 91501-970 Porto Alegre, RS, BrazilMicroelectronics Group, INF, Federal University of Rio Grande do Sul, Avenida Bento Gonçalves 9500, P.O. Box 15064, 91501-970 Porto Alegre, RS, BrazilMicroelectronics Group, INF, Federal University of Rio Grande do Sul, Avenida Bento Gonçalves 9500, P.O. Box 15064, 91501-970 Porto Alegre, RS, BrazilMicroelectronics Group, INF, Federal University of Rio Grande do Sul, Avenida Bento Gonçalves 9500, P.O. Box 15064, 91501-970 Porto Alegre, RS, BrazilGroup of Architectures and Integrated Circuits, CDTEC, Federal University of Pelotas, Campus Universitário s/n, P.O. Box 354, 96001-970 Pelotas, RS, BrazilMicroelectronics Group, INF, Federal University of Rio Grande do Sul, Avenida Bento Gonçalves 9500, P.O. Box 15064, 91501-970 Porto Alegre, RS, BrazilIn the rate-distortion optimization (RDO), the process of choosing the best prediction mode is performed through exhaustive executions of the whole encoding process, increasing significantly the encoder computational complexity. Considering H.264/AVC intra frame prediction, there are several modes to encode a macroblock (MB). This work proposes an algorithm and the hardware design for a fast intra frame mode decision module for H.264/AVC encoders. The application of the proposed algorithm reduces in more than 10 times the number of encoding iterations for choosing the best intramode when compared with RDO-based decision. The architecture was synthesized to FPGA and achieved an operation frequency of 98 MHz processing more than 300 HD1080p frames per second. With this approach, we achieved one order-of-magnitude performance improvement compared with RDO-based approaches, which is very important not only from the performance but also from the energy consumption perspective for battery-operated devices. In order to compare the architecture with previously published works, we also synthesized it to standard cells. Compared with the best previous results reported, the implemented architecture achieves a complexity reduction of five times, a processing capability increase of 14 times, and a reduction in the number of clock cycles per MB of 11 times.http://dx.doi.org/10.1155/2012/813023 |
| spellingShingle | Daniel Palomino Guilherme Corrêa Cláudio Diniz Sergio Bampi Luciano Agostini Altamiro Susin Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders International Journal of Reconfigurable Computing |
| title | Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders |
| title_full | Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders |
| title_fullStr | Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders |
| title_full_unstemmed | Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders |
| title_short | Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders |
| title_sort | algorithm and hardware design of a fast intra frame mode decision module for h 264 avc encoders |
| url | http://dx.doi.org/10.1155/2012/813023 |
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