Thermal stress behavior and optimization of solder joints in CSP-LED packages
This study explores the thermal stress behavior of chip-scale LED (CSP-LED) packages with a focus on micro/nanoscale interfacial effects and thermal transport under rapid temperature cycling. Finite element analysis (FEA), combined with advanced Taguchi optimization, identifies critical stress zones...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2025-06-01
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| Series: | Results in Engineering |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2590123025007893 |
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| Summary: | This study explores the thermal stress behavior of chip-scale LED (CSP-LED) packages with a focus on micro/nanoscale interfacial effects and thermal transport under rapid temperature cycling. Finite element analysis (FEA), combined with advanced Taguchi optimization, identifies critical stress zones and evaluates the impact of void ratio, chip substrate material, solder layer thickness, and PCB substrate material on solder joint reliability. Results reveal that maximum equivalent stress concentrates at the solder layer's outer corners due to thermal mismatch. Key findings include the dominant role of PCB substrate material and microstructural void configurations in affecting interfacial stress. Optimal conditions, such as a void ratio of 0 %, a ceramic PCB, and a 40 μm solder layer, significantly enhance mechanical reliability. These insights contribute to advanced thermal management strategies for CSP-LEDs and other high-power electronics. |
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| ISSN: | 2590-1230 |