Speeding Up FPGA Placement via Partitioning and Multithreading
One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The...
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| Main Author: | |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2009-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2009/514754 |
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