A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier
Approximate computing is an emerging and effective method for reducing energy consumption in digital circuits, which is critical for energy-efficient performance improvement of edge-computing devices. In this paper, we propose a low-power DNN accelerator with novel signed approximate multiplier base...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
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| Online Access: | https://ieeexplore.ieee.org/document/10500495/ |
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| author | Laimin Du Leibin Ni Xiong Liu Guanqi Peng Kai Li Wei Mao Hao Yu |
| author_facet | Laimin Du Leibin Ni Xiong Liu Guanqi Peng Kai Li Wei Mao Hao Yu |
| author_sort | Laimin Du |
| collection | DOAJ |
| description | Approximate computing is an emerging and effective method for reducing energy consumption in digital circuits, which is critical for energy-efficient performance improvement of edge-computing devices. In this paper, we propose a low-power DNN accelerator with novel signed approximate multiplier based on probability-optimized compressor and error compensation. The probability-optimized compressor is customized for partial product matrix (PPM) of signed operands, which gets the optimal logic circuit after probabilistic analysis and optimization. At the same time, we explored the PPM truncation method, found out the impact of different partial product (PP) truncation numbers on circuit benefit and error, and achieved a more ideal performance-error tradeoff through a reasonable error compensation method. In the optimal case of 8 bits, the proposed approximate multiplier saves 49.84% power, 46.41% area and 24.65% delay compared to the exact multiplier. We employed the proposed approximate multiplier in the vector systolic array as the processing element (PE). Under the VGG-16 evaluation, the proposed accelerator achieves performance improvement of energy efficiency <inline-formula> <tex-math notation="LaTeX">$1.96\times $ </tex-math></inline-formula>, while the error loss was only 0.95%. |
| format | Article |
| id | doaj-art-0c4573592ae6437fa46e2fd2968417bd |
| institution | Kabale University |
| issn | 2644-1225 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj-art-0c4573592ae6437fa46e2fd2968417bd2025-01-21T00:02:44ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252024-01-015576810.1109/OJCAS.2023.327925110500495A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed MultiplierLaimin Du0https://orcid.org/0000-0003-3119-3805Leibin Ni1https://orcid.org/0000-0002-5480-3146Xiong Liu2Guanqi Peng3https://orcid.org/0009-0001-7379-1494Kai Li4https://orcid.org/0000-0003-3251-931XWei Mao5https://orcid.org/0000-0003-2527-6778Hao Yu6https://orcid.org/0000-0002-2674-4118School of Microelectronics, Southern University of Science and Technology, Shenzhen, Guangdong, ChinaAdvanced Computing and Storage Laboratory, Huawei Technologies Company Ltd., Shenzhen, Guangdong, ChinaSchool of Advanced Manufacturing, Fuzhou University, Fuzhou, Fujian, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, Guangdong, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, Guangdong, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, Guangdong, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, Guangdong, ChinaApproximate computing is an emerging and effective method for reducing energy consumption in digital circuits, which is critical for energy-efficient performance improvement of edge-computing devices. In this paper, we propose a low-power DNN accelerator with novel signed approximate multiplier based on probability-optimized compressor and error compensation. The probability-optimized compressor is customized for partial product matrix (PPM) of signed operands, which gets the optimal logic circuit after probabilistic analysis and optimization. At the same time, we explored the PPM truncation method, found out the impact of different partial product (PP) truncation numbers on circuit benefit and error, and achieved a more ideal performance-error tradeoff through a reasonable error compensation method. In the optimal case of 8 bits, the proposed approximate multiplier saves 49.84% power, 46.41% area and 24.65% delay compared to the exact multiplier. We employed the proposed approximate multiplier in the vector systolic array as the processing element (PE). Under the VGG-16 evaluation, the proposed accelerator achieves performance improvement of energy efficiency <inline-formula> <tex-math notation="LaTeX">$1.96\times $ </tex-math></inline-formula>, while the error loss was only 0.95%.https://ieeexplore.ieee.org/document/10500495/Approximate computingmultipliercompressorprobability analysistruncationvector |
| spellingShingle | Laimin Du Leibin Ni Xiong Liu Guanqi Peng Kai Li Wei Mao Hao Yu A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier IEEE Open Journal of Circuits and Systems Approximate computing multiplier compressor probability analysis truncation vector |
| title | A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier |
| title_full | A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier |
| title_fullStr | A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier |
| title_full_unstemmed | A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier |
| title_short | A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier |
| title_sort | low power dnn accelerator with mean error minimized approximate signed multiplier |
| topic | Approximate computing multiplier compressor probability analysis truncation vector |
| url | https://ieeexplore.ieee.org/document/10500495/ |
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