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    Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips

    Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips by Dan LIU, Yi FENG, Xiang-lei DANG, Dong TONG, Xu CHENG, Ke-yi WANG

    Published 2012-11-01
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  2. 2
    Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips

    Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips by Dan LIU, Yi FENG, Xiang-lei DANG, Dong TONG, Xu CHENG, Ke-yi WANG

    Published 2012-11-01
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    Article
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