Guidelines for Organic Handling Requirements for Citrus Packinghouses and Processors by James J. Ferguson, Mark A. Ritenour

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Guidelines for Organic Handling Requirements for Citrus Packinghouses and Processors by James J. Ferguson, Mark A. Ritenour

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An Educational RISC-V-Based 16-Bit Processor by Jecel Mattos de Assumpção, Oswaldo Hideo Ando, Hugo Puertas de Araújo, Mario Gazziro

“…This work introduces a novel custom-designed 16-bit RISC-V processor, intended for educational purposes and for use in low-resource equipment. …”
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NVPE: An FPGA-Based Non-Volatile Processor Emulator for Intermittent Computing by Idris Somoye, Kevin Yang

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Circuit-Based Leakage-to-Erasure Conversion in a Neutral-Atom Quantum Processor by Matthew N. H. Chow, Vikas Buchemmavari, Sivaprasad Omanakuttan, Bethany J. Little, Saurabh Pandey, Ivan H. Deutsch, Yuan-Yu Jau

“…This circuit-based leakage-to-erasure error conversion is a critical component of a neutral-atom quantum processor where the quantum information may significantly outlive the lifetime of any individual atom in the quantum register. …”
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System Verification and FPGA Implementation of Hardware Preemptive Scheduler for RISC-V Processor by Ionel Zagan, Vasile Gheorghita Gaitan

“…In soft-core processor implementations based on software schedulers, there is an overhead that should not be neglected in HARD and FIRM real-time systems (RTS). …”
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Study of Register Value Branch Predictor Based on CNN by Yingjie Tang, Zhangjin Chen, Wuyi Fang

“…In modern processor architecture, a branch predictor is an important module whose design influences the performance of the processor. …”
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Fast implementations of ARX-based lightweight block ciphers (SPARX, CHAM) on 32-bit processor by Byoungjin Seok, Changhoon Lee

“…However, if the word size of a block cipher is smaller than the register size of the target device, it may process inefficiently in the aspect of memory usage. …”
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System Level Design of Reconfigurable Server Farms Using Elliptic Curve Cryptography Processor Engines by Sangook Moon, Jongsu Park

“…In the design of the elliptic curve cryptography processor engine, we propose a 3X faster GF(2m) serial multiplication architecture.…”
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Method for designing specialized computing systems based on hardware and software co-optimization by I. Е. Tarasov, P. N. Sovietov, D. V. Lulyava, D. I. Mirzoyan

“…Among computing node architectures, a synchronous pipeline and a processor core with a tree-like arithmetic-logical unit are considered. …”
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Quantum Hardware Devices (QHDs): Opportunities and Challenges by Aziz Oukaira

“…This review focuses on the core building blocks of quantum computing qubits, quantum gates, registers, and chipsets, while emphasizing the pivotal role of advanced architectures, such as Field-Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs), in optimizing quantum information processing. …”
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ML-Driven Transistor Self-Heating Analysis From TCAD to Large IP Circuits by Simon Thomann, Nico Mayr, Albi Mema, Hussam Amrouch

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Quantum computing architecture with trapped ion crystals and fast Rydberg gates by Han Bao, Jonas Vogel, Ulrich Poschinger, Ferdinand Schmidt-Kaler

“…The proposed gate operation is ready to be combined with a scalable processor architecture to reconfigure the qubit register, either by shuttling ions or by dynamically controlling optical tweezer potentials.…”
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Method for designing specialized computing systems on the basis of hardware and software cooptimization by I. E. Tarasov, P. N. Sovietov, D. V. Lulyava, N. A. Duksin

“…On the basis of pipeline structures, a number of algorithms can be implemented to effectively complement programmable processor devices and provide hardware acceleration of some tasks. …”
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Verifiable measurement-based quantum random sampling with trapped ions by Martin Ringbauer, Marcel Hinsche, Thomas Feldker, Paul K. Faehrmann, Juani Bermejo-Vega, Claire L. Edmunds, Lukas Postler, Roman Stricker, Christian D. Marciniak, Michael Meth, Ivan Pogorelov, Rainer Blatt, Philipp Schindler, Jens Eisert, Thomas Monz, Dominik Hangleiter

“…Here, we experimentally demonstrate efficiently verifiable quantum random sampling in the measurement-based model of quantum computation on a trapped-ion quantum processor. We create and sample from random cluster states, which are at the heart of measurement-based computing, up to a size of 4 × 4 qubits. …”
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Retrieval of top-of-atmosphere fluxes from combined EarthCARE lidar, imager, and broadband radiometer observations: the BMA-FLX product by A. Velázquez Blázquez, C. Domenech, E. Baudrez, N. Clerbaux, C. Salas Molar, N. Madenach

“…A combined flux, derived from co-registered radiances at the reference level, is provided as the best estimate for a given scene. …”
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Demonstration of Fault-Tolerant Steane Quantum Error Correction by Lukas Postler, Friederike Butt, Ivan Pogorelov, Christian D. Marciniak, Sascha Heußen, Rainer Blatt, Philipp Schindler, Manuel Rispler, Markus Müller, Thomas Monz

“…The Steane QEC method involves preparing an auxiliary logical qubit of the same QEC code as used for the data register. The data and auxiliary registers are then coupled with a logical controlled-not (cnot) gate, enabling a measurement of the auxiliary register to reveal the error syndrome. …”
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Port-Based State Preparation and Applications by Garazi Muguruza, Florian Speelman

“…As an application, we introduce approximate Universal Programmable Hybrid Processors (UPHP). Here the goal is to encode a unitary as a quantum state, and the UPHP can apply this unitary to a quantum state when knowing its classical description. …”
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Quantum state preparation for multivariate functions by Matthias Rosenkranz, Eric Brunner, Gabriel Marin-Sanchez, Nathan Fitzpatrick, Silas Dilkes, Yao Tang, Yuta Kikuchi, Marcello Benedetti

“…A fundamental step of any quantum algorithm is the preparation of qubit registers in a suitable initial state. Often qubit registers represent a discretization of continuous variables and the initial state is defined by a multivariate function. …”
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Exponential optimization of adiabatic quantum-state preparation by Davide Cugini, Davide Nigro, Mattia Bruno, Dario Gerace

“…The preparation of a given quantum state on a quantum computing register is a typically demanding operation, requiring a number of elementary gates that scales exponentially with the size of the problem. …”
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