Efficient sparse state preparation via quantum walks by Alvin Gonzales, Rebekah Herrman, Colin Campbell, Igor Gaidai, Ji Liu, Teague Tomesh, Zain H. Saleem

“…Our approach utilizes combinatorics techniques such as minimal hitting sets, minimum spanning trees, and shortest Hamiltonian paths to reduce the number of controlled gates required to prepare sparse states. …”
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Modular line-selector unit for enabling selective-scan driving in conventional oxide TFT scan drivers by Minjae Jeong, Young Wook Kim, Ki Taeg Shin, Hoon Jeong, Jeong Ki Park, Hyun Jae Kim

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A Self-Tuning Variable Universe Fuzzy PID Control Framework with Hybrid BAS-PSO-SA Optimization for Unmanned Surface Vehicles by Huixia Zhang, Zhao Zhao, Yuchen Wei, Yitong Liu, Wenyang Wu

“…The experimental validation under wind and wave disturbances shows that the heading deviation is less than 0.0392°, meeting the IMO MSC.1/Circ.1580 standard, and an 89.5% improvement in energy efficiency. Although the processing time is 12.7% longer compared to the GRO approach, this framework lays a solid foundation for ship autonomy systems, and future enhancements will focus on MPC-based time delay compensation and Field-Programmable Gate Array (FPGA) acceleration.…”
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Unifying Non-Markovian Characterization with an Efficient and Self-Consistent Framework by G. A. L. White, P. Jurcevic, C. D. Hill, K. Modi

“…Finally, we conclude our analysis with applications thereof to the efficacy of control techniques to counteract these effects—including noise-aware circuit compilation and optimized dynamical decoupling. …”
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Rise of conditionally clean ancillae for efficient quantum circuit constructions by Tanuj Khattar, Craig Gidney

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An Accelerated FPGA-Based Parallel CNN-LSTM Computing Device by Xin Zhou, Wei Xie, Han Zhou, Yongjing Cheng, Ximing Wang, Yun Ren, Shandong Yuan, Liuwen Li

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Resource-efficient shadow tomography using equatorial stabilizer measurements by Guedong Park, Yong Siah Teo, Hyunseok Jeong

“…Our scheme only requires an n-depth controlled-Z (CZ) circuit [O(n^{2}) CZ gates] and Pauli measurements per sampling copy. …”
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Embedded Hardware-Efficient FPGA Architecture for SVM Learning and Inference by B. B. Shabarinath, Muralidhar Pullakandam

“…A configuration signal turns on corresponding sub-blocks and clock-gating unused ones, thus enhancing resource utilization efficiency, energy efficiency, and overall performance. …”
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A Simple and Robust Solid-State Circuit Breaker for Low Voltage DC Applications by Rezoana Sharmin Riana, Sajib Biswas Shuvo, Abdul Jabber Antor, Muhammad Abdullah Arafat

“…The proposed design utilizes a silicon controlled rectifier (SCR) thyristor as the main switch, which is turned off by a MOSFET during a fault condition. …”
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T‐depth reduction method for efficient SHA‐256 quantum circuit construction by Jongheon Lee, Sokjoon Lee, You‐Seok Lee, Dooho Choi

“…In this paper, the authors propose a novel technique to reduce T‐depth (and T‐count) when some quantum circuits located in between two Toffoli‐gates are interchangeable with a controlled phase gate (CP gate), and the authors apply this technique to five types of quantum adders, reducing T‐depth by more than 33%. …”
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A High-Speed, Multi-Channel Lossless Compression Algorithm for High-Resolution Video on FPGA by Xingkai Du, Longhua Xie, Hongchuan Huang, Huawei Chen, Xiaolong Guo, Tingyu Zhao

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TOP: A Combined Logical and Physical Obfuscation Method for Securing Networks-on-Chip Against Reverse Engineering Attacks by Mona Hashemi, Siamak Mohammadi, Trevor E. Carlson

“…TOP operates using security keys to assume control of network components and reconfigure its structure and routing paths, utilizing existing units designed for use by power-gating controllers. …”
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An Efficiency Multiplexing Scheme and Improved Sampling Method for Multichannel Data Acquisition System by Chengqun Chu, Yongfeng Ren, Xin Liu, Yongqiu Zheng, Wei Fang

“…And then, a simple improved sampling control method is also employed to improve the performance. …”
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A rapid and efficient strategy for combinatorial repression of multiple genes in Escherichia coli by Yi Zheng, Yuxia Mo, Yingbo Yuan, Tianyuan Su, Qingsheng Qi

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HyperSense: Hyperdimensional Intelligent Sensing for Energy‐Efficient Sparse Data Processing by Sanggeon Yun, Hanning Chen, Ryozo Masukawa, Hamza Errahmouni Barkam, Andrew Ding, Wenjun Huang, Arghavan Rezvani, Shaahin Angizi, Mohsen Imani

“…Introducing HyperSense, the co‐designed hardware and software system efficiently controls analog‐to‐digital converter (ADC) modules’ data generation rate based on object presence predictions in sensor data. …”
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Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard usi... by Muhammad Ovais Akhter, Najam Muhammad Amin, Razia Zia

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GTrXL-SAC-Based Path Planning and Obstacle-Aware Control Decision-Making for UAV Autonomous Control by Jingyi Huang, Yujie Cui, Guipeng Xi, Shuangxia Bai, Bo Li, Geng Wang, Evgeny Neretin

“…Research on UAV (unmanned aerial vehicle) path planning and obstacle avoidance control based on DRL (deep reinforcement learning) still faces limitations, as previous studies primarily utilized current perceptual inputs while neglecting the continuity of flight processes, resulting in low early-stage learning efficiency. …”
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A New Hybrid Intelligent Method for Accurate Short Term Electric Power Production Forecasting From Uncertain Renewable Energy Resources by Gholamreza Memarzadeh, Farshid Keynia, Faezeh Amirteimoury, Rasoul Memarzadeh, Hossein Noori

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A DSP–FPGA Heterogeneous Accelerator for On-Board Pose Estimation of Non-Cooperative Targets by Qiuyu Song, Kai Liu, Shangrong Li, Mengyuan Wang, Junyi Wang

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Exploring Dynamics and Hardware Implementation of an Enhanced 5D Hyperchaotic Memristive System Inspired by Sprott-C System by Abdulmajeed Abdullah Mohammed Mokbel, Fei Yu, Yumba Musoya Gracia, Bohong Tan, Hairong Lin, Herbert Ho-Ching Iu

“…Then, the flexibility and efficiency of the real-time operating environment were demonstrated, and the system was actually implemented on a field-programmable gate array (FPGA) hardware platform. …”
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