Correction: Hsieh et al. Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits.... by Tung-Ying Hsieh, Ping-Yi Hsieh, Chih-Chao Yang, Chang-Hong Shen, Jia-Min Shieh, Wen-Kuan Yeh, Meng-Chyi Wu

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Ge N‐Channel Ferroelectric FET Memory With Al2O3/AlN Interfacial Layer by Microwave Annealing by Sheng‐Yen Zheng, Wei‐Ning Kao, Yu‐Hsing Chen, Yung‐Hsien Wu

“…The proposed IL and low thermal budget of MWA alleviate element diffusion and reduce oxygen vacancies, marking the first demonstration of Ge n‐FeFET memory devices controlled by dipoles. …”
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Demonstration of Vertically Stacked ZnO/Te Complementary Field‐Effect Transistor by Kiyung Kim, Minjae Kim, Yongsu Lee, Hae‐Won Lee, Jae Hyeon Jun, Jun‐Hyeok Choi, Seongbeen Yoon, Hyeon‐Jun Hwang, Byoung Hun Lee

“…The proposed ZnO/Te CFET can be a promising device technology, particularly for 3D and heterojunction integration requiring a low thermal budget.…”
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