Showing 1 - 15 results of 15 for search '"full adder."', query time: 0.04s Refine Results
  1. 1
    Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic)

    Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic) by D. Satyanarayana, M. Chennakesavulu, N. Fouzia Sulthana, K. Upendra, D. Sashidhar, K. Ramachandra Reddy, N. Naga Sai Vikranth, V. Devendra

    Published 2025-06-01
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  2. 2
    Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

    Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell by Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour

    Published 2022-09-01
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  3. 3
    Feasibility of Cascadable Plasmonic Full Adder

    Feasibility of Cascadable Plasmonic Full Adder by Mitsuo Fukuda, Ryo Watanabe, Yuta Tonooka, Masashi Ota

    Published 2019-01-01
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  4. 4
    Compact XOR/XNOR-Based Adders and BNNs Utilizing Drain-Erase Scheme in Ferroelectric FETs

    Compact XOR/XNOR-Based Adders and BNNs Utilizing Drain-Erase Scheme in Ferroelectric FETs by Musaib Rafiq, Yogesh Singh Chauhan, Shubham Sahay

    Published 2025-01-01
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  5. 5
    High-Speed Current-Mode Full-Adder with Carbon Nanotube Technology

    High-Speed Current-Mode Full-Adder with Carbon Nanotube Technology by Mehdi Habibollahi, Ali Saghafinia

    Published 2024-04-01
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  6. 6
    Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs

    Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs by Hyundong Lee, Seonghoon Kim, Jongbeom Kim, Jaehoon Jeong, Jeonggyu Yang, Taigon Song

    Published 2025-01-01
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  7. 7
    CNTFET-Based Design of a High-Efficient Full Adder Using XOR Logic

    CNTFET-Based Design of a High-Efficient Full Adder Using XOR Logic by Seyedehsomayeh Hatefinasab

    Published 2016-12-01
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  8. 8
    COMPREHENSIVE ANALYSIS OF COST FUNCTION IN QUANTUM-DOT CELLULAR AUTOMATA

    COMPREHENSIVE ANALYSIS OF COST FUNCTION IN QUANTUM-DOT CELLULAR AUTOMATA by Esam Alkaldy, Ali Majeed, Salam M. Atiyah, Ahmed Wisam Obaid

    Published 2025-04-01
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  9. 9
    CNTFET Based Pseudo Ternary Adder Design and Simulation

    CNTFET Based Pseudo Ternary Adder Design and Simulation by Mousa Yousefi, Zainab Moradi, Khalil Monfaredi

    Published 2022-12-01
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  10. 10
    Low Latency and Power Efficient Reversible Full Adder based on Toffoli Gates

    Low Latency and Power Efficient Reversible Full Adder based on Toffoli Gates by Seyedeh Fatemeh Deymad, Nabiollah Shiri, Farshad Pesaran

    Published 2025-04-01
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  11. 11
    FPGA‐Based Design of Ultra‐Efficient Approximate Adders for High‐Fidelity Image Processing: A Logic‐Optimized Approach

    FPGA‐Based Design of Ultra‐Efficient Approximate Adders for High‐Fidelity Image Processing: A Logic‐Optimized Approach by Ramakrishna Reddy Eamani, N. Vinodhkumar, Ambe Harrison, Wulfran Fendzi Mbasso

    Published 2025-07-01
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  12. 12
    A Novel Full Subtractor /Full Adder Design in Quantum Cellular Automata

    A Novel Full Subtractor /Full Adder Design in Quantum Cellular Automata by Mostafa Sadeghi, Keivan Navi, Mehdi Dolatshahi

    Published 2024-02-01
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  13. 13
    Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions

    Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions by Zahra Mehdizadeh Taheri, Sayed Masoud Sayedi, Mohammad Hossein Moaiyeri

    Published 2025-01-01
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  14. 14
    Efficient 22 nm GNRFET PTLA using low power trimode technique for high speed processor

    Efficient 22 nm GNRFET PTLA using low power trimode technique for high speed processor by Sneha Arora, Suman Lata Tripathi, Inung Wijayanto, Sobhit Saxena

    Published 2025-04-01
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  15. 15
    Stateful Full Adder Using Silicon Diodes

    Stateful Full Adder Using Silicon Diodes by Jaemin Son, Juhee Jeon, Kyoungah Cho, Sangsig Kim

    Published 2025-06-01
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