Statistical Timing Analysis for Subthreshold Circuit Based on Bayesian Inference by Donglin Liu, Yuping Wu, Zhiqiang Li, Xuelian Zhang, Xi Tian

“…Accurately predicting the delay distribution of subthreshold circuits is crucial for verifying the timing closure of digital circuits and estimating parameter yields. The delay variation, which is the parameter of delay distribution, is not independent of the adjacent cells, because of the input conversion changes caused by the previous gate, making it difficult to model and estimate. …”
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Efficient design of non-restoring parity-preserving reversible divider by Mohammad Talebi, Mohammad Mosleh, Mohsen Chekin

“…<p>One of the basic challenges in high-density integrated circuits is loss of power consumption, which is caused by presence of transistors in circuits and causes the temperature of the circuit to increase. The design of digital circuits in a reversible way can be used as one of efficient approaches to solve this challenge. …”
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A fault tolerant CSA in QCA technology for IoT devices by Saeid Seyedi, Hatam Abdoli

“…The proposed CSA will increase the robustness and reliability of QCA-based digital circuits by integrating fault tolerance into its design such that the circuitry based on QCA can keep their functionality on even in fault-prone environments.…”
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Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications by Venkata Sudhakar Chowdam, Suresh Babu Potladurty, Prasad Reddy karipireddy

“…Although approximation arithmetic affects the output accuracy in multipliers, it offers a realistic avenue for constructing power-, area--, and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. …”
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