-
1
Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m)
Published 2021-05-01Subjects: Get full text
Article -
2
Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors
Published 2021-05-01Subjects: Get full text
Article -
3
Accessible interactive learning of missing-digit arithmetic problems for students with visual disabilities
Published 2025-05-01Subjects: Get full text
Article