LHCA: a new low-power, high-speed carry skip adder using hybrid memristor-MOS logic by Ramesh Kumar, Bal Chand Nagar

Subjects: “…Adder…”
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An efficient method of modulo adder design for Digital Signal Processing applications by Subodh Kumar Singhal, Sumit Kumar, Sujit Kumar Patel, K. Anjali Rao, Gaurav Saxena

Subjects: “…Diminished-1 modulo adder…”
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CNTFET Based Pseudo Ternary Adder Design and Simulation by Mousa Yousefi, Zainab Moradi, Khalil Monfaredi

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Low Latency and Power Efficient Reversible Full Adder based on Toffoli Gates by Seyedeh Fatemeh Deymad, Nabiollah Shiri, Farshad Pesaran

Subjects: “…ripple carry adder…”
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Redistribution of Signals Power in Multipath System of Radio Communication by W. I. Kaganov, F. Ki

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Design of a low-delay 4-bit parallel prefix adder using QCA technology by Tushar Niranjan, Anirban Nayak, Sreehari Veeramachaneni, Syed Ershad Ahmed

Subjects: “…Parallel prefix adder…”
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THE ELECTROMAGNETIC FIELD STRUCTURE IN THE SECTORIAL RESONATOR by Yu. A. Krasnitsky

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Comparative analysis of adders hardware implementation on FPGA by Nikolay Ivanovich Chervyakov, Pavel Alekseyevich Lyakhov, Maria Vasilevna Valueva, O. V. Krivolapova

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Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic) by D. Satyanarayana, M. Chennakesavulu, N. Fouzia Sulthana, K. Upendra, D. Sashidhar, K. Ramachandra Reddy, N. Naga Sai Vikranth, V. Devendra

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MINI Logic 1-Bit Adder: A Comparison with Hybrid NMOS-Memristor-Logic Styles Using Ta2O5/Al2O3 Based RRAM Device by NITHYA, N., PARAMASIVAM, K.

Subjects: “…adder…”
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Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell by Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour

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Energy efficient design and implementation of approximate adder for image processing applications by Naik Jatothu Brahmaiah, Kumar Kanagala Sateesh, Krishnaiah Kondragunta Rama, Koteswararao Seelam

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Feasibility of Cascadable Plasmonic Full Adder by Mitsuo Fukuda, Ryo Watanabe, Yuta Tonooka, Masashi Ota

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Optimized low power hybrid adder architecture for OFDM in wireless communication by T. Kalavathi Devi, E. B. Priyanka, R. Anand, G. B. Bhavana, P. Sakthivel, S. Thangavel, Baseem Khan, K. Jeyanthi

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Allocation of Resources to Growth and Spore Production in a Fern Ophioglossum vulgatum L.: Effects of Mowing and Simulated Herbivory by Natalia Jędrzejczak, Paweł Olejniczak, Zbigniew Celka

Subjects: “…adder's‐tongue fern…”
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Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOI by Jeff Dix

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Compact XOR/XNOR-Based Adders and BNNs Utilizing Drain-Erase Scheme in Ferroelectric FETs by Musaib Rafiq, Yogesh Singh Chauhan, Shubham Sahay

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Simulation and Performance Analysis of 32 nm FinFet based 4-Bit Carry Look Adder by S. Rashid, S. Khan, A. Singh

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A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology by Ali Ghorbani, Mehdi Dolatshahi, S. Mohammadali Zanjani, Behrang Barekatain

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A quantum multiplier based on the quantum Fourier transform algorithm by Qian Junkai, Zhu Jialiang, Ye Bin

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