PAGR: Accelerating Global Routing for VLSI Design Flow by Roman A. Solovyev, Ilya A. Mkrtchan, Dmitry V. Telpukhov, Ilya I. Shafeev, Aleksandr Y. Romanov, Yevgeniy V. Stolbikov, Alexander L. Stempkovsky

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A New Statistical Method for Maximum Power Estimation in CMOS VLSI Circuits by N. E. Evmorfopoulos, J. N. Avaritsiotis

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VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders by Georgios Passas, Steven Freear

“…The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. …”
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A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique by Trong-Tu Bui, Tadashi Shibata

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An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates by T. Kalavathi Devi, Sakthivel Palaniappan

“…At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. …”
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FPGA‐based implementation of floating point processing element for the design of efficient FIR filters by Tintu Mary John, Shanty Chacko

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Obfuscation of combination circuits of digital devices from unauthorized access by L. A. Zolotorevich

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Canonization of graphs during transistor circuits decompilation by D. I. Cheremisinov, L. D. Cheremisinova

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Application of decision diagrams of incompletely specified of k-valued logic functions in the synthesis of logical circuits by P. N. Bibilo

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An Overview of Hybrid DC–DC Converters: From Seeds to Leaves by Yan Lu, Junwei Huang, Zhiguo Tong, Tingxu Hu, Wen-Liang Zeng, Mo Huang, Xiangyu Mao, Guigang Cai

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Controlling Underwater Robots with Electronic Nervous Systems by Joseph Ayers, Nikolai Rulkov, Dan Knudsen, Yong-Bin Kim, Alexander Volkovskii, Allen Selverston

“…We report feasibility studies of a hybrid architecture that instantiates a command and coordinating level with computed discrete-time map-based (DTM) neuronal networks and the central pattern generators with analogue VLSI (Very Large Scale Integration) electronic neuron (aVLSI) networks. …”
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Review and Selection Strategy for High-Accuracy Modeling of PWM Converters in DCM by Yu-Jun Mao, Chi-Seng Lam, Sai-Weng Sin, Man-Chung Wong, Rui Paulo Martins

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Implementation of Special Function Unit for Vertex Shader Processor Using Hybrid Number System by Avni Agarwal, P. Harsha, Swati Vasishta, S. Sivanantham

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Si1−xGex nanowire based metal‐semiconductor‐metal Schottky biristor: Design and sensitivity analysis by Shaleen Nr, Sangeeta Singh, Pankaj Kumar

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Saliency-Based Bleeding Localization for Wireless Capsule Endoscopy Diagnosis by Hongda Chen, Shaoze Wang, Yong Ding, Dahong Qian

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Estimation and Statistical Analysis of Human Voice Parameters to Investigate the Influence of Psychological Stress and to Determine the Vocal Tract Transfer Function of an Individu... by Puneet Kumar Mongia, R. K. Sharma

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A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS by Nabihah Ahmad, Rezaul Hasan

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Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model by Shupeng Wang, Kai Huang, Tianyi Xie, Xiaolang Yan

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A 12 dB 0.7 V 𝟖𝟓𝟎𝝁W CMOS LNA for 866 MHz UHF RFID Reader by Jie Li, S. M. Rezaul Hasan

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MULTIPLE FOLDING OF REGULAR STRUCTURES VIA SOLVING LOGIC EQUATIONS by L. D. Cheremisinova

“…The problem under consideration is to reduce the area of the layout of regular VLSI structures by means of their multiple folding. …”
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