A Readout Scheme for PCM-Based Analog In-Memory Computing With Drift Compensation Through Reference Conductance Tracking by Alessio Antolini, Andrea Lico, Francesco Zavalloni, Eleonora Franchi Scarselli, Antonio Gnudi, Mattia Luigi Torres, Roberto Canegallo, Marco Pasotti

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Editorial Special Section on High-Performance Frequency Synthesizers by Salvatore Levantino, Wanghua Wu

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A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL by Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers

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High-Speed Wireline Links—Part II: Optimization and Performance Assessment by Hossein Shakiba, Davide Tonietto, Ali Sheikholeslami

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How to Design a Differential CMOS <italic>LC</italic> Oscillator by Asad A. Abidi, David Murphy

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Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers by Michael Peter Kennedy, Xu Lu, Xu Wang

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Terahertz Light-Field Imaging With Silicon Technologies by U. R. Pfeiffer, A. Kutaish

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Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth by Tetsuya Iizuka, Ritaro Takenaka, Hao Xu, Asad A. Abidi

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High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects by Joo-Hyung Chae

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A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS by Lucas Moura Santana, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx

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Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With &#x0394;&#x03A3; Quantization Cancellation by Yizhe Hu, Weichen Tao, Robert Bogdan Staszewski

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High-Speed Wireline Links&#x2014;Part I: Modeling by Hossein Shakiba, Davide Tonietto, Ali Sheikholeslami

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Challenges and Innovations in CMOS-Based 300-GHz Transceivers for High-Speed Wireless Communication by Minoru Fujishima

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A &#x2212;11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology by Yongxin Li, Tianyu Wang, Mostafa Gamal Ahmed, Ruhao Xia, Kyu-Sang Park, Mahmoud A. Khalil, Sashank Krishnamurthy, Zhe Xuan, Ganesh Balamurugan, Pavan Kumar Hanumolu

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SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology by Rajiv V. Joshi, J. Frougier, Alberto Cestero, Crystal Castellanos, Sudipto Chakraborty, Carl Radens, M. Silvestre, S. Lucarini, I. Ahsan, E. Leobandung

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Enhancing RF Fingerprint Generation in Power Amplifiers: Unequally Spaced Multitone Design Approaches and Considerations by Chengyu Fan, Junting Deng, Ethan Chen, Vanessa Chen

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Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers by Seoyoung Jang, Jaewon Lee, Yujin Choi, Donggeun Kim, Gain Kim

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An Overview of Hybrid DC&#x2013;DC Converters: From Seeds to Leaves by Yan Lu, Junwei Huang, Zhiguo Tong, Tingxu Hu, Wen-Liang Zeng, Mo Huang, Xiangyu Mao, Guigang Cai

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The Problem of Spurious Emissions in 5G FR2 Phased Arrays, and a Solution Based on an Upmixer With Embedded LO Leakage Cancellation by Arun Paidimarri, Yujiro Tojo, Caglar Ozdag, Alberto Valdes-Garcia, Bodhisatwa Sadhu

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High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions by Shenggao Li, Mu-Shan Lin, Wei-Chih Chen, Chien-Chun Tsai

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