112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems by Henry Park, Mohammed Abdullatif, Ehung Chen, Tamer Ali

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Si Substrate Backside—An Emerging Physical Attack Surface for Secure ICs in Flip Chip Packaging by Makoto Nagata, Takuji Miki

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Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications by Ahmad Khairi, Amir Laufer, Ilia Radashkevich, Yoel Krupnik, Jihwan Kim, Tali Warshavsky Grafi, Ajay Balankutty, Yaniv Sabag, Yoav Segal, Udi Virobnik, Mike Peng Li, Itamar Levin, Yosef Ben Ezra, Ariel Cohen

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A Survey of Computing-in-Memory Processor: From Circuit to Application by Wenyu Sun, Jinshan Yue, Yifan He, Zongle Huang, Jingyu Wang, Wenbin Jia, Yaolei Li, Luchang Lei, Hongyang Jia, Yongpan Liu

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SAR-Assisted Energy-Efficient Hybrid ADCs by Kent Edrian Lozada, Dong-Jin Chang, Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu

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Digital Phase-Locked Loops: Exploring Different Boundaries by Yuncheng Zhang, Dingxin Xu, Kenichi Okada

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Review on Resistive Termination Techniques Driven by Wireline Channel Behaviors by Changjae Moon, Minsoo Choi, Myungguk Lee, Byungsub Kim

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8-Shaped Inductors: An Essential Addition to RFIC Designers’ Toolbox by Pingda Guan, Haikun Jia, Wei Deng, Teerachot Siriburanon, Robert Bogdan Staszewski, Zhihua Wang, Baoyong Chi

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Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s by Liping Zhong, Quan Pan

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Timing-Skew Calibration Techniques in Time-Interleaved ADCs by Mingyang Gu, Yunsong Tao, Yi Zhong, Lu Jie, Nan Sun

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Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques by Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski

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Ultra-Wideband 4-Bit Distributed Phase Shifters Using Lattice Network at <italic>K/Ka</italic>- and <italic>E/W</italic>-Band by Sungwon Kwon, Minjae Jung, Byung-Wook Min

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A Readout Scheme for PCM-Based Analog In-Memory Computing With Drift Compensation Through Reference Conductance Tracking by Alessio Antolini, Andrea Lico, Francesco Zavalloni, Eleonora Franchi Scarselli, Antonio Gnudi, Mattia Luigi Torres, Roberto Canegallo, Marco Pasotti

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Editorial Special Section on High-Performance Frequency Synthesizers by Salvatore Levantino, Wanghua Wu

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A&#x2013;102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL by Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers

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High-Speed Wireline Links&#x2014;Part II: Optimization and Performance Assessment by Hossein Shakiba, Davide Tonietto, Ali Sheikholeslami

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How to Design a Differential CMOS <italic>LC</italic> Oscillator by Asad A. Abidi, David Murphy

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Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers by Michael Peter Kennedy, Xu Lu, Xu Wang

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Terahertz Light-Field Imaging With Silicon Technologies by U. R. Pfeiffer, A. Kutaish

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Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth by Tetsuya Iizuka, Ritaro Takenaka, Hao Xu, Asad A. Abidi

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