Showing 1 - 3 results of 3 for search '"DPLL"', query time: 0.02s Refine Results
  1. 1
    A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation

    A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation by Waleed Madany, Yuncheng Zhang, Ashbir Aviat Fadila, Hongye Huang, Junjun Qiu, Jill Mayeda, Atsushi Shirane, Kenichi Okada

    Published 2025-01-01
    Subjects:
    Get full text
    Article
    Save to List
    Saved in:
  2. 2
    Experimental research of transient processes in firmware digital phase-locked loop

    Experimental research of transient processes in firmware digital phase-locked loop by А. П. Бондарев, С. И. Алтунин

    Published 2016-10-01
    Subjects:
    Get full text
    Article
    Save to List
    Saved in:
  3. 3
    Subcarrier synchronization for satellite USB TT&C

    Subcarrier synchronization for satellite USB TT&C by Zhang Shiwei, Xing Sirui, Chang Junde, Jin Yuting, Zhao Bo, Shen Chenyang

    Published 2022-05-01
    Subjects: “…digital phase-locked loop(dpll)…”
    Get full text
    Article
    Save to List
    Saved in:

Search Tools: