Ultrawideband LNA 1960–2019: Review by Shahab Shahrabadi

“…This article specifically studies the challenges and solutions of designing UWB LNA by reviewing topologies and techniques such as inductive peaking, noise and distortion cancellation, gm‐boosting, active inductor and notch filter. …”
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A 1–5 GHz 22 mW receiver frontend with active‐feedback baseband and voltage‐commutating mixers in 65 nm CMOS by Benqing Guo, Haishi Wang, Huifen Wang, Lei Li, Wanting Zhou, Kianoosh Jalali

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Development and Efficiency Analysis of Dual Active Bridge Converter Employing SiC Devices Using TMS 320F280039 by T. Deepti, K. Deepa, Albert Alexander Stonier, Geno Peter, A. Anoop, Vivekananda Ganji

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An efficient loop tiling framework for convolutional neural network inference accelerators by Hongmin Huang, Xianghong Hu, Xueming Li, Xiaoming Xiong

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Ultra‐stable, low‐noise two‐stage current source concept for electronics and laser applications by Grzegorz Dudzik

“…The obtained parameters are competitive to commercial current drivers designed for laser applications. The two‐stage current source has been successfully implemented in a fully integrated diode‐pumped solid‐state lasers.…”
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Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology by Anil Singh, Veena Rawat, Alpana Agarwal

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Voltage Reference and Voltage Regulator for the Cryogenic Performance Evaluation of the 22nm FDSOI Technology by Alfonso R. Cabrera-Galicia, Arun Ashok, Patrick Vliex, Andre Kruth, Andre Zambanini, Stefan van Waasen

“…Additionally, we report the impact that MOS transistor cryogenic phenomena have over these circuits and propose to take advantage of some of those phenomena in analog circuit design. …”
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A Low-Power Streaming Speech Enhancement Accelerator for Edge Devices by Ci-Hao Wu, Tian-Sheuan Chang

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A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction by Yu-Ping Huang, Yu-Sian Lu, Wei-Zen Chen

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A Radar-Based System for Detection of Human Fall Utilizing Analog Hardware Architectures of Decision Tree Model by Vassilis Alimisis, Dimitrios G. Arnaoutoglou, Emmanouil Anastasios Serlis, Argyro Kamperi, Konstantinos Metaxas, George A. Kyriacou, Paul P. Sotiriadis

“…The architectures were trained using Python and were compared to software-based classifiers. The circuit designs were executed using TSMC’s 90 nm CMOS process technology and the Cadence IC Suite was employed for tasks including design, schematic implementation, and post-layout simulations.…”
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V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation by Chao Wang, Yicong Shao, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao, Wei Mao, Yongfu Li

“…These strengths underscore its significant impact and applicability in the domain of circuit design.…”
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Analysis and Verilog-A Modeling of Floating-Gate Transistors by Sayma Nowshin Chowdhury, Matthew Chen, Sahil Shah

“…Floating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. Designing and fabricating these circuits typically involves extensive SPICE-based simulations, yet integrating and calibrating floating-gate transistors post-fabrication is a common practice. …”
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A Companding Technique to Reduce Peak-to-Average Ratio in Discrete Multitone Wireline Receivers by Miad Laghaei, Hossein Shakiba, Ali Sheikholeslami

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A Wireless Power Conversion Chain With Fully On-Chip Automatic Resonance Tuning System for Biomedical Implants by Mohammad Javad Karimi, Menghe Jin, Catherine Dehollain, Alexandre Schmid

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A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI by Jhoan Salinas, Hossein Shakiba, Ali Sheikholeslami

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Computation of Graph Fourier Transform Centrality Using Graph Filter by Chien-Cheng Tseng, Su-Ling Lee

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Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutions by Kamilya Smagulova, Mohammed E. Fouda, Ahmed Eltawil

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FBMC vs. PAM and DMT for High-Speed Wireline Communication by Jeremy Cosson-Martin, Jhoan Salinas, Hossein Shakiba, Ali Sheikholeslami

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A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing by Manish Srivastava, Alessandro Ferro, Aleksandr Sidun, Jose M. De La Rosa, Kilian O'Donoghue, Padraig Cantillon-Murphy, Daniel O'Hare

“…This enables a single low-dropout (LDO) voltage regulator to generate both power supply and <inline-formula> <tex-math notation="LaTeX">$\text{V}_{ref}$ </tex-math></inline-formula> for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula> consumes <inline-formula> <tex-math notation="LaTeX">$300 ~\mu \text{W}$ </tex-math></inline-formula> of power when clocked at 10.24 MHz. …”
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112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems by Henry Park, Mohammed Abdullatif, Ehung Chen, Tamer Ali

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