Enhanced AODV routing analysis for mobile Ad Hoc networks
Abstract Ad-hoc wireless networks entail efficient and scalable routing protocols to support real-time, low-latency communication in dynamic environments. Conventional routing algorithms such as ad-hoc on-demand distance vector (AODV) frequently struggle with hardware inefficiencies and increase ove...
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| Format: | Article |
| Language: | English |
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Springer
2025-05-01
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| Series: | Discover Electronics |
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| Online Access: | https://doi.org/10.1007/s44291-025-00069-8 |
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| author | Arvind Kumar Adesh Kumar Anurag Vijay Agrawal |
| author_facet | Arvind Kumar Adesh Kumar Anurag Vijay Agrawal |
| author_sort | Arvind Kumar |
| collection | DOAJ |
| description | Abstract Ad-hoc wireless networks entail efficient and scalable routing protocols to support real-time, low-latency communication in dynamic environments. Conventional routing algorithms such as ad-hoc on-demand distance vector (AODV) frequently struggle with hardware inefficiencies and increase overhead in large-scale networks. To address these limitations, the research paper emphasizes a novel hardware design of a homogenous clustered HMC-AODV routing that is personalized with FPGA implementation to enhance routing efficiency and performance. The protocol optimizes hardware utilization and improves network performance compared to the standard AODV protocol by organizing nodes into small clusters. The performance of the routing chip is evaluated by integrating Zedboard field programmable gate array (FPGA) based on hardware metrics such as input/output blocks (IoBs), flip-flops, slices, look-up tables (LUTs), and memory utilization with a network size of 64 nodes. The anticipated HMC-AODV protocol shows improvements over existing protocols in terms of end-to-end delay (E2E delay) and controls overhead by a reduction of 10.4% to 25.1% and 8.9% to 35.4% respectively with the maximum frequency support of 286 MHz and, packet delivery ratio (PDR) = 1.0. The FPGA-based design reduces power consumption and maximizes routing efficiency which makes it an ideal choice for real-time applications. |
| format | Article |
| id | doaj-art-ff4e8dc19b4341b184f3872dc05a1dba |
| institution | OA Journals |
| issn | 2948-1600 |
| language | English |
| publishDate | 2025-05-01 |
| publisher | Springer |
| record_format | Article |
| series | Discover Electronics |
| spelling | doaj-art-ff4e8dc19b4341b184f3872dc05a1dba2025-08-20T02:00:02ZengSpringerDiscover Electronics2948-16002025-05-012111310.1007/s44291-025-00069-8Enhanced AODV routing analysis for mobile Ad Hoc networksArvind Kumar0Adesh Kumar1Anurag Vijay Agrawal2Department of Electrical and Electronics Engineering, School of Advanced Engineering, UPESDepartment of Electrical and Electronics Engineering, School of Advanced Engineering, UPESDepartment of Electronics and Communication Engineering, Bhagwant Institute of TechnologyAbstract Ad-hoc wireless networks entail efficient and scalable routing protocols to support real-time, low-latency communication in dynamic environments. Conventional routing algorithms such as ad-hoc on-demand distance vector (AODV) frequently struggle with hardware inefficiencies and increase overhead in large-scale networks. To address these limitations, the research paper emphasizes a novel hardware design of a homogenous clustered HMC-AODV routing that is personalized with FPGA implementation to enhance routing efficiency and performance. The protocol optimizes hardware utilization and improves network performance compared to the standard AODV protocol by organizing nodes into small clusters. The performance of the routing chip is evaluated by integrating Zedboard field programmable gate array (FPGA) based on hardware metrics such as input/output blocks (IoBs), flip-flops, slices, look-up tables (LUTs), and memory utilization with a network size of 64 nodes. The anticipated HMC-AODV protocol shows improvements over existing protocols in terms of end-to-end delay (E2E delay) and controls overhead by a reduction of 10.4% to 25.1% and 8.9% to 35.4% respectively with the maximum frequency support of 286 MHz and, packet delivery ratio (PDR) = 1.0. The FPGA-based design reduces power consumption and maximizes routing efficiency which makes it an ideal choice for real-time applications.https://doi.org/10.1007/s44291-025-00069-8MANETHardware chipAODVFPGANodeRouting |
| spellingShingle | Arvind Kumar Adesh Kumar Anurag Vijay Agrawal Enhanced AODV routing analysis for mobile Ad Hoc networks Discover Electronics MANET Hardware chip AODV FPGA Node Routing |
| title | Enhanced AODV routing analysis for mobile Ad Hoc networks |
| title_full | Enhanced AODV routing analysis for mobile Ad Hoc networks |
| title_fullStr | Enhanced AODV routing analysis for mobile Ad Hoc networks |
| title_full_unstemmed | Enhanced AODV routing analysis for mobile Ad Hoc networks |
| title_short | Enhanced AODV routing analysis for mobile Ad Hoc networks |
| title_sort | enhanced aodv routing analysis for mobile ad hoc networks |
| topic | MANET Hardware chip AODV FPGA Node Routing |
| url | https://doi.org/10.1007/s44291-025-00069-8 |
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