Simulation Study on Switching Process and Reverse Recovery Performance of Low Miller Capacitance Super Junction MOSFET
For super junction field effect transistor (SJ-MOSFET), two device structures with different p-pillar morphology of multiple epitaxial ion implantation and deep groove etching were established. The static characteristics of SJ-MOS with different processes and gate structures were compared and studie...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
Editorial Department of Electric Drive for Locomotives
2021-09-01
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| Series: | 机车电传动 |
| Subjects: | |
| Online Access: | http://edl.csrzic.com/thesisDetails#10.13890/j.issn.1000-128x.2021.05.006 |
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| Summary: | For super junction field effect transistor (SJ-MOSFET), two device structures with different p-pillar morphology of multiple epitaxial ion implantation and deep groove etching were established. The static characteristics of SJ-MOS with different processes and gate structures were compared and studied, and compared with the measured data to verify the correctness of the model.From the perspective of uneven expansion of space charge region, the micro mechanism of "capacitance turning" phenomenon in <italic>C</italic>-<italic>V</italic> characteristic test of devices with different process routes was analyzed. Then, the variation of gate voltage, drain current and drain source voltage with time in the switching process of SJ-MOS under inductive load was studied. Finally, a parasitic diode reverse recovery test platform was built to explore the effects of different processes on parameters such as reverse recovery charge and peak current. The research content of this paper could guide the device design to a certain extent and improve the matching degree of power semiconductor devices in locomotive application scenarios. |
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| ISSN: | 1000-128X |