Hardware Efficient Architecture with Variable Block Size for Motion Estimation
Video coding standards such as MPEG-x and H.26x incorporate variable block size motion estimation (VBSME) which is highly time consuming and extremely complex from hardware implementation perspective due to huge computation. In this paper, we have discussed basic aspects of video coding and studied...
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| Format: | Article |
| Language: | English |
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Wiley
2016-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2016/5091519 |
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| author | Nehal N. Shah Harikrishna Singapuri Upena D. Dalal |
| author_facet | Nehal N. Shah Harikrishna Singapuri Upena D. Dalal |
| author_sort | Nehal N. Shah |
| collection | DOAJ |
| description | Video coding standards such as MPEG-x and H.26x incorporate variable block size motion estimation (VBSME) which is highly time consuming and extremely complex from hardware implementation perspective due to huge computation. In this paper, we have discussed basic aspects of video coding and studied and compared existing architectures for VBSME. Various architectures with different pixel scanning pattern give a variety of performance results for motion vector (MV) generation, showing tradeoff between macroblock processed per second and resource requirement for computation. Aim of this paper is to design VBSME architecture which utilizes optimal resources to minimize chip area and offer adequate frame processing rate for real time implementation. Speed of computation can be improved by accessing 16 pixels of base macroblock of size 4 × 4 in single clock cycle using z scanning pattern. Widely adopted cost function for hardware implementation known as sum of absolute differences (SAD) is used for VBSME architecture with multiplexer based absolute difference calculator and partial summation term reduction (PSTR) based multioperand adders. Device utilization of proposed implementation is only 22k gates and it can process 179 HD (1920 × 1080) resolution frames in best case and 47 HD resolution frames in worst case per second. Due to such higher throughput design is well suitable for real time implementation. |
| format | Article |
| id | doaj-art-ff090252b94d414289561b9146d83cc3 |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2016-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-ff090252b94d414289561b9146d83cc32025-02-03T01:20:46ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552016-01-01201610.1155/2016/50915195091519Hardware Efficient Architecture with Variable Block Size for Motion EstimationNehal N. Shah0Harikrishna Singapuri1Upena D. Dalal2Sarvajanik College of Engineering and Technology, Surat, IndiaS V National Institute of Technology, Surat, IndiaS V National Institute of Technology, Surat, IndiaVideo coding standards such as MPEG-x and H.26x incorporate variable block size motion estimation (VBSME) which is highly time consuming and extremely complex from hardware implementation perspective due to huge computation. In this paper, we have discussed basic aspects of video coding and studied and compared existing architectures for VBSME. Various architectures with different pixel scanning pattern give a variety of performance results for motion vector (MV) generation, showing tradeoff between macroblock processed per second and resource requirement for computation. Aim of this paper is to design VBSME architecture which utilizes optimal resources to minimize chip area and offer adequate frame processing rate for real time implementation. Speed of computation can be improved by accessing 16 pixels of base macroblock of size 4 × 4 in single clock cycle using z scanning pattern. Widely adopted cost function for hardware implementation known as sum of absolute differences (SAD) is used for VBSME architecture with multiplexer based absolute difference calculator and partial summation term reduction (PSTR) based multioperand adders. Device utilization of proposed implementation is only 22k gates and it can process 179 HD (1920 × 1080) resolution frames in best case and 47 HD resolution frames in worst case per second. Due to such higher throughput design is well suitable for real time implementation.http://dx.doi.org/10.1155/2016/5091519 |
| spellingShingle | Nehal N. Shah Harikrishna Singapuri Upena D. Dalal Hardware Efficient Architecture with Variable Block Size for Motion Estimation Journal of Electrical and Computer Engineering |
| title | Hardware Efficient Architecture with Variable Block Size for Motion Estimation |
| title_full | Hardware Efficient Architecture with Variable Block Size for Motion Estimation |
| title_fullStr | Hardware Efficient Architecture with Variable Block Size for Motion Estimation |
| title_full_unstemmed | Hardware Efficient Architecture with Variable Block Size for Motion Estimation |
| title_short | Hardware Efficient Architecture with Variable Block Size for Motion Estimation |
| title_sort | hardware efficient architecture with variable block size for motion estimation |
| url | http://dx.doi.org/10.1155/2016/5091519 |
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