Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips

Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips

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Existing methods for clock domain crossing (CDC) design were used directly in a system-on-chip (SoC),which result in high design and verification complexity.To solve this problem,a design method was proposed.It separated CDC design completely from functional design and transmits all the CDC signals...

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Bibliographic Details
Main Authors: Dan LIU, Yi FENG, Xiang-lei DANG, Dong TONG, Xu CHENG, Ke-yi WANG
Format: Article
Language:zho
Published: Editorial Department of Journal on Communications 2012-11-01
Series:Tongxin xuebao
Subjects:
system-on-chip
clock domain crossing design
verification complexity
communication interface
Online Access:http://www.joconline.com.cn/zh/article/doi/10.3969/j.issn.1000-436x.2012.11.019/
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