Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips
Existing methods for clock domain crossing (CDC) design were used directly in a system-on-chip (SoC),which result in high design and verification complexity.To solve this problem,a design method was proposed.It separated CDC design completely from functional design and transmits all the CDC signals...
Saved in:
| Main Authors: | , , , , , |
|---|---|
| Format: | Article |
| Language: | zho |
| Published: |
Editorial Department of Journal on Communications
2012-11-01
|
| Series: | Tongxin xuebao |
| Subjects: | |
| Online Access: | http://www.joconline.com.cn/zh/article/doi/10.3969/j.issn.1000-436x.2012.11.019/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1841539888078389248 |
|---|---|
| author | Dan LIU Yi FENG Xiang-lei DANG Dong TONG Xu CHENG Ke-yi WANG |
| author_facet | Dan LIU Yi FENG Xiang-lei DANG Dong TONG Xu CHENG Ke-yi WANG |
| author_sort | Dan LIU |
| collection | DOAJ |
| description | Existing methods for clock domain crossing (CDC) design were used directly in a system-on-chip (SoC),which result in high design and verification complexity.To solve this problem,a design method was proposed.It separated CDC design completely from functional design and transmits all the CDC signals in an IP design with the help of an independent and dedicated CDC processing module.It also scaled down the total number of CDC signals to two groups of opposite directions through encapsulating point-to-point communication interface as well as processing CDC signals of the same direction in combination.Experiment results demonstrate that this method is able to sharply reduce the verification complexity of CDC design and also simplify the whole SoC design,without significant adding to transfer delay or area cost of an IP design. |
| format | Article |
| id | doaj-art-fe7690edf528489b92c926eef8d6901a |
| institution | Kabale University |
| issn | 1000-436X |
| language | zho |
| publishDate | 2012-11-01 |
| publisher | Editorial Department of Journal on Communications |
| record_format | Article |
| series | Tongxin xuebao |
| spelling | doaj-art-fe7690edf528489b92c926eef8d6901a2025-01-14T06:33:35ZzhoEditorial Department of Journal on CommunicationsTongxin xuebao1000-436X2012-11-013315115859666936Method for reducing the complexity of clock domain crossing design and its verification in system-on-chipsDan LIUYi FENGXiang-lei DANGDong TONGXu CHENGKe-yi WANGExisting methods for clock domain crossing (CDC) design were used directly in a system-on-chip (SoC),which result in high design and verification complexity.To solve this problem,a design method was proposed.It separated CDC design completely from functional design and transmits all the CDC signals in an IP design with the help of an independent and dedicated CDC processing module.It also scaled down the total number of CDC signals to two groups of opposite directions through encapsulating point-to-point communication interface as well as processing CDC signals of the same direction in combination.Experiment results demonstrate that this method is able to sharply reduce the verification complexity of CDC design and also simplify the whole SoC design,without significant adding to transfer delay or area cost of an IP design.http://www.joconline.com.cn/zh/article/doi/10.3969/j.issn.1000-436x.2012.11.019/system-on-chipclock domain crossing designverification complexitycommunication interface |
| spellingShingle | Dan LIU Yi FENG Xiang-lei DANG Dong TONG Xu CHENG Ke-yi WANG Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips Tongxin xuebao system-on-chip clock domain crossing design verification complexity communication interface |
| title | Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips |
| title_full | Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips |
| title_fullStr | Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips |
| title_full_unstemmed | Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips |
| title_short | Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips |
| title_sort | method for reducing the complexity of clock domain crossing design and its verification in system on chips |
| topic | system-on-chip clock domain crossing design verification complexity communication interface |
| url | http://www.joconline.com.cn/zh/article/doi/10.3969/j.issn.1000-436x.2012.11.019/ |
| work_keys_str_mv | AT danliu methodforreducingthecomplexityofclockdomaincrossingdesignanditsverificationinsystemonchips AT yifeng methodforreducingthecomplexityofclockdomaincrossingdesignanditsverificationinsystemonchips AT xiangleidang methodforreducingthecomplexityofclockdomaincrossingdesignanditsverificationinsystemonchips AT dongtong methodforreducingthecomplexityofclockdomaincrossingdesignanditsverificationinsystemonchips AT xucheng methodforreducingthecomplexityofclockdomaincrossingdesignanditsverificationinsystemonchips AT keyiwang methodforreducingthecomplexityofclockdomaincrossingdesignanditsverificationinsystemonchips |