Floorplacement for Partial Reconfigurable FPGA-Based Systems
We presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Our work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2011-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2011/483681 |
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| _version_ | 1850162154182803456 |
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| author | A. Montone M. D. Santambrogio F. Redaelli D. Sciuto |
| author_facet | A. Montone M. D. Santambrogio F. Redaelli D. Sciuto |
| author_sort | A. Montone |
| collection | DOAJ |
| description | We presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Our work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities, and wirelength. Task graphs with few externally connected RRs lead to the biggest decrease, while external wirelength in task graphs with many externally connected RRs show lower improvement. The proposed approach results, as also demonstrated in the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven approaches and a highly increased probability of reuse of existing links (90% reduction can be obtained in the best case). |
| format | Article |
| id | doaj-art-fce0a4269fdd45a1bc9deccf677e4e9d |
| institution | OA Journals |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2011-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-fce0a4269fdd45a1bc9deccf677e4e9d2025-08-20T02:22:38ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092011-01-01201110.1155/2011/483681483681Floorplacement for Partial Reconfigurable FPGA-Based SystemsA. Montone0M. D. Santambrogio1F. Redaelli2D. Sciuto3Dipartimento di Elettronica e Informazione, Politecnico di Milano, 20133 Milano, ItalyDipartimento di Elettronica e Informazione, Politecnico di Milano, 20133 Milano, ItalyDipartimento di Elettronica e Informazione, Politecnico di Milano, 20133 Milano, ItalyDipartimento di Elettronica e Informazione, Politecnico di Milano, 20133 Milano, ItalyWe presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Our work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities, and wirelength. Task graphs with few externally connected RRs lead to the biggest decrease, while external wirelength in task graphs with many externally connected RRs show lower improvement. The proposed approach results, as also demonstrated in the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven approaches and a highly increased probability of reuse of existing links (90% reduction can be obtained in the best case).http://dx.doi.org/10.1155/2011/483681 |
| spellingShingle | A. Montone M. D. Santambrogio F. Redaelli D. Sciuto Floorplacement for Partial Reconfigurable FPGA-Based Systems International Journal of Reconfigurable Computing |
| title | Floorplacement for Partial Reconfigurable FPGA-Based Systems |
| title_full | Floorplacement for Partial Reconfigurable FPGA-Based Systems |
| title_fullStr | Floorplacement for Partial Reconfigurable FPGA-Based Systems |
| title_full_unstemmed | Floorplacement for Partial Reconfigurable FPGA-Based Systems |
| title_short | Floorplacement for Partial Reconfigurable FPGA-Based Systems |
| title_sort | floorplacement for partial reconfigurable fpga based systems |
| url | http://dx.doi.org/10.1155/2011/483681 |
| work_keys_str_mv | AT amontone floorplacementforpartialreconfigurablefpgabasedsystems AT mdsantambrogio floorplacementforpartialreconfigurablefpgabasedsystems AT fredaelli floorplacementforpartialreconfigurablefpgabasedsystems AT dsciuto floorplacementforpartialreconfigurablefpgabasedsystems |