Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic
Dynamic partial reconfiguration (DPR) allows us to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, we present two new DPR systems that allow for efficient implementations of 1D FIR filters on modern FPGA devices. To minimize the required...
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| Format: | Article |
| Language: | English |
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Wiley
2010-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2010/357978 |
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| _version_ | 1832553439565971456 |
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| author | Daniel Llamocca Marios Pattichis G. Alonzo Vera |
| author_facet | Daniel Llamocca Marios Pattichis G. Alonzo Vera |
| author_sort | Daniel Llamocca |
| collection | DOAJ |
| description | Dynamic partial reconfiguration (DPR) allows us to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, we present two new DPR systems that allow for efficient implementations of 1D FIR filters on modern FPGA devices. To minimize the required partial reconfiguration region (PRR), both implementations are based on distributed arithmetic. For a smaller required PRR, the first system only allows changes to the filter coefficient values while keeping the rest of the architecture fixed. The second DPR system allows full FIR-filter reconfiguration while requiring a larger PR region. We investigate the proposed system performance in terms of the dynamic reconfiguration rates. At low reconfiguration rates, the DPR systems can maintain much higher throughputs. We also present an example that demonstrates that the system can maintain a throughput of 10 Mega-samples per second while fully reconfiguring about seventy times per second. |
| format | Article |
| id | doaj-art-f99add32e35743209730c9e94565ee04 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2010-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-f99add32e35743209730c9e94565ee042025-02-03T05:54:02ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092010-01-01201010.1155/2010/357978357978Partial Reconfigurable FIR Filtering System Using Distributed ArithmeticDaniel Llamocca0Marios Pattichis1G. Alonzo Vera2Electrical and Computer Engineering Department, The University of New Mexico, Albuquerque, NM 87131, USAElectrical and Computer Engineering Department, The University of New Mexico, Albuquerque, NM 87131, USAMicroelectronics Research and Development Corporation, Albuquerque, NM 87110, USADynamic partial reconfiguration (DPR) allows us to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, we present two new DPR systems that allow for efficient implementations of 1D FIR filters on modern FPGA devices. To minimize the required partial reconfiguration region (PRR), both implementations are based on distributed arithmetic. For a smaller required PRR, the first system only allows changes to the filter coefficient values while keeping the rest of the architecture fixed. The second DPR system allows full FIR-filter reconfiguration while requiring a larger PR region. We investigate the proposed system performance in terms of the dynamic reconfiguration rates. At low reconfiguration rates, the DPR systems can maintain much higher throughputs. We also present an example that demonstrates that the system can maintain a throughput of 10 Mega-samples per second while fully reconfiguring about seventy times per second.http://dx.doi.org/10.1155/2010/357978 |
| spellingShingle | Daniel Llamocca Marios Pattichis G. Alonzo Vera Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic International Journal of Reconfigurable Computing |
| title | Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic |
| title_full | Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic |
| title_fullStr | Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic |
| title_full_unstemmed | Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic |
| title_short | Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic |
| title_sort | partial reconfigurable fir filtering system using distributed arithmetic |
| url | http://dx.doi.org/10.1155/2010/357978 |
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