VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding
Motion estimation (ME) is the most computationally intensive task in video encoding. This study proposes a full‐search variable‐block‐size ME for the high‐efficiency video coding or H.265 specification. The proposed method reduces memory requirements to a large extent by following a Morton order for...
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| Format: | Article |
| Language: | English |
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Wiley
2017-11-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/iet-cds.2016.0267 |
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| author | Niras Cheeckottu Vayalil Yinan Kong |
| author_facet | Niras Cheeckottu Vayalil Yinan Kong |
| author_sort | Niras Cheeckottu Vayalil |
| collection | DOAJ |
| description | Motion estimation (ME) is the most computationally intensive task in video encoding. This study proposes a full‐search variable‐block‐size ME for the high‐efficiency video coding or H.265 specification. The proposed method reduces memory requirements to a large extent by following a Morton order for data reading and a sum of absolute differences reuse strategy. The data bandwidth demand is also diminished by broadcasting data into multiple processing elements. This ME accelerator supports variable‐block‐size prediction blocks ranging from 8×4 to 64×64, and is reconfigurable in various search ranges for a trade‐off between performance and area. The proposed method for very‐large‐scale integration (VLSI) architecture is synthesized with 32 nm technology, and is capable of real‐time encoding of ultra‐high‐definition (4K‐UHD, at 30 Hz) video with a search range of 64 pixels in both horizontal and vertical directions, operating at a frequency of 282 MHz. |
| format | Article |
| id | doaj-art-f70f3bdc246c4a3e862d3f2ddd0b2e9c |
| institution | OA Journals |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2017-11-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-f70f3bdc246c4a3e862d3f2ddd0b2e9c2025-08-20T02:22:49ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982017-11-0111654354810.1049/iet-cds.2016.0267VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video EncodingNiras Cheeckottu Vayalil0Yinan Kong1Department of EngineeringMacquarie UniversitySydney2109NSWAustraliaDepartment of EngineeringMacquarie UniversitySydney2109NSWAustraliaMotion estimation (ME) is the most computationally intensive task in video encoding. This study proposes a full‐search variable‐block‐size ME for the high‐efficiency video coding or H.265 specification. The proposed method reduces memory requirements to a large extent by following a Morton order for data reading and a sum of absolute differences reuse strategy. The data bandwidth demand is also diminished by broadcasting data into multiple processing elements. This ME accelerator supports variable‐block‐size prediction blocks ranging from 8×4 to 64×64, and is reconfigurable in various search ranges for a trade‐off between performance and area. The proposed method for very‐large‐scale integration (VLSI) architecture is synthesized with 32 nm technology, and is capable of real‐time encoding of ultra‐high‐definition (4K‐UHD, at 30 Hz) video with a search range of 64 pixels in both horizontal and vertical directions, operating at a frequency of 282 MHz.https://doi.org/10.1049/iet-cds.2016.0267frequency 282 MHzvertical directionshorizontal directions4K-UHDreal-time ultra-high-definitionVHDL |
| spellingShingle | Niras Cheeckottu Vayalil Yinan Kong VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding IET Circuits, Devices and Systems frequency 282 MHz vertical directions horizontal directions 4K-UHD real-time ultra-high-definition VHDL |
| title | VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding |
| title_full | VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding |
| title_fullStr | VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding |
| title_full_unstemmed | VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding |
| title_short | VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding |
| title_sort | vlsi architecture of full search variable block size motion estimation for hevc video encoding |
| topic | frequency 282 MHz vertical directions horizontal directions 4K-UHD real-time ultra-high-definition VHDL |
| url | https://doi.org/10.1049/iet-cds.2016.0267 |
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