All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
Abstract Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-01-01
|
| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cds2.12000 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832559664962732032 |
|---|---|
| author | Lanhua Xia Jifei Tang |
| author_facet | Lanhua Xia Jifei Tang |
| author_sort | Lanhua Xia |
| collection | DOAJ |
| description | Abstract Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital built‐in self‐test structure of CP‐PLL especially suitable for low‐cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP‐PLL under test. It reduces the requirement of additional external test clocks and high‐performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%. |
| format | Article |
| id | doaj-art-f4a029022d09420b8f6679a40282f41d |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2021-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-f4a029022d09420b8f6679a40282f41d2025-02-03T01:29:38ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982021-01-0115111010.1049/cds2.12000All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loopsLanhua Xia0Jifei Tang1School of Communication Engineering Hangzhou Dianzi University Hangzhou Zhejiang Province ChinaSchool of Communication Engineering Hangzhou Dianzi University Hangzhou Zhejiang Province ChinaAbstract Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital built‐in self‐test structure of CP‐PLL especially suitable for low‐cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP‐PLL under test. It reduces the requirement of additional external test clocks and high‐performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.https://doi.org/10.1049/cds2.12000built‐in self testcalibrationintegrated circuit testingphase locked loopssystem‐on‐chipvoltage‐controlled oscillators |
| spellingShingle | Lanhua Xia Jifei Tang All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops IET Circuits, Devices and Systems built‐in self test calibration integrated circuit testing phase locked loops system‐on‐chip voltage‐controlled oscillators |
| title | All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops |
| title_full | All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops |
| title_fullStr | All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops |
| title_full_unstemmed | All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops |
| title_short | All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops |
| title_sort | all digital built in self test scheme for charge pump phase locked loops |
| topic | built‐in self test calibration integrated circuit testing phase locked loops system‐on‐chip voltage‐controlled oscillators |
| url | https://doi.org/10.1049/cds2.12000 |
| work_keys_str_mv | AT lanhuaxia alldigitalbuiltinselftestschemeforchargepumpphaselockedloops AT jifeitang alldigitalbuiltinselftestschemeforchargepumpphaselockedloops |