Memory Map: A Multiprocessor Cache Simulator
Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses t...
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| Format: | Article |
| Language: | English |
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Wiley
2012-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2012/365091 |
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| _version_ | 1832560149046231040 |
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| author | Shaily Mittal Nitin |
| author_facet | Shaily Mittal Nitin |
| author_sort | Shaily Mittal |
| collection | DOAJ |
| description | Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses to shared memory. An important characteristic of any system design process is memory configuration and data flow management. Although, it is very important to select a correct memory configuration, it might be equally imperative to choreograph the data flow between various levels of memory in an optimal manner. Memory map is a multiprocessor simulator to choreograph data flow in individual caches of multiple processors and shared memory systems. This simulator allows user to specify cache reconfigurations and number of processors within the application program and evaluates cache miss and hit rate for each configuration phase taking into account reconfiguration costs. The code is open source and in java. |
| format | Article |
| id | doaj-art-eee1bde64dab45d08bea4ad229184084 |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-eee1bde64dab45d08bea4ad2291840842025-02-03T01:28:19ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552012-01-01201210.1155/2012/365091365091Memory Map: A Multiprocessor Cache SimulatorShaily Mittal0Nitin1Department of Computer Science & Engineering, Chitkara University, Baddi, Solan 174103, IndiaDepartment of Computer Science & Engineering and Information Technology, Jaypee University of Information Technology, Waknaghat, Solan 173234, IndiaNowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses to shared memory. An important characteristic of any system design process is memory configuration and data flow management. Although, it is very important to select a correct memory configuration, it might be equally imperative to choreograph the data flow between various levels of memory in an optimal manner. Memory map is a multiprocessor simulator to choreograph data flow in individual caches of multiple processors and shared memory systems. This simulator allows user to specify cache reconfigurations and number of processors within the application program and evaluates cache miss and hit rate for each configuration phase taking into account reconfiguration costs. The code is open source and in java.http://dx.doi.org/10.1155/2012/365091 |
| spellingShingle | Shaily Mittal Nitin Memory Map: A Multiprocessor Cache Simulator Journal of Electrical and Computer Engineering |
| title | Memory Map: A Multiprocessor Cache Simulator |
| title_full | Memory Map: A Multiprocessor Cache Simulator |
| title_fullStr | Memory Map: A Multiprocessor Cache Simulator |
| title_full_unstemmed | Memory Map: A Multiprocessor Cache Simulator |
| title_short | Memory Map: A Multiprocessor Cache Simulator |
| title_sort | memory map a multiprocessor cache simulator |
| url | http://dx.doi.org/10.1155/2012/365091 |
| work_keys_str_mv | AT shailymittal memorymapamultiprocessorcachesimulator AT nitin memorymapamultiprocessorcachesimulator |