Multi-FPGA Partitioning Method Based on Topological Levelization
This paper presents a partitioning method based on topological ordering and levelization. The proposed method, termed RPL, performs multi-FPGA partitioning by taking into account six different partitioning constraints. We also compare RPL to two existing algorithms. The first approach is a hierarchi...
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| Format: | Article |
| Language: | English |
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Wiley
2010-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2010/709487 |
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| _version_ | 1832546775299260416 |
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| author | Nabil Kerkiz Amr Elchouemi Don Bouldin |
| author_facet | Nabil Kerkiz Amr Elchouemi Don Bouldin |
| author_sort | Nabil Kerkiz |
| collection | DOAJ |
| description | This paper presents a partitioning method based on topological ordering and levelization. The proposed method, termed RPL, performs multi-FPGA partitioning by taking into account six different partitioning constraints. We also compare RPL to two existing algorithms. The first approach is a hierarchical partitioning method based on topological ordering (HP). The second approach is a recursive algorithm based on the Fiduccia and Mattheyses bipartitioning heuristic (RP). Experimental results on seven application benchmarks mapped onto three different hardware architectures demonstrated that the proposed RPL approach achieved fewer partitions in less time when compared to the RP and HP algorithms. |
| format | Article |
| id | doaj-art-ec513a6c53fc455f9c71b563271dd737 |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2010-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-ec513a6c53fc455f9c71b563271dd7372025-02-03T06:47:24ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552010-01-01201010.1155/2010/709487709487Multi-FPGA Partitioning Method Based on Topological LevelizationNabil Kerkiz0Amr Elchouemi1Don Bouldin2Electrical & Computer Engineering, University of Tennessee at Knoxville, TN 37996, USAElectrical & Computer Engineering, University of Tennessee at Knoxville, TN 37996, USAElectrical & Computer Engineering, University of Tennessee at Knoxville, TN 37996, USAThis paper presents a partitioning method based on topological ordering and levelization. The proposed method, termed RPL, performs multi-FPGA partitioning by taking into account six different partitioning constraints. We also compare RPL to two existing algorithms. The first approach is a hierarchical partitioning method based on topological ordering (HP). The second approach is a recursive algorithm based on the Fiduccia and Mattheyses bipartitioning heuristic (RP). Experimental results on seven application benchmarks mapped onto three different hardware architectures demonstrated that the proposed RPL approach achieved fewer partitions in less time when compared to the RP and HP algorithms.http://dx.doi.org/10.1155/2010/709487 |
| spellingShingle | Nabil Kerkiz Amr Elchouemi Don Bouldin Multi-FPGA Partitioning Method Based on Topological Levelization Journal of Electrical and Computer Engineering |
| title | Multi-FPGA Partitioning Method Based on Topological Levelization |
| title_full | Multi-FPGA Partitioning Method Based on Topological Levelization |
| title_fullStr | Multi-FPGA Partitioning Method Based on Topological Levelization |
| title_full_unstemmed | Multi-FPGA Partitioning Method Based on Topological Levelization |
| title_short | Multi-FPGA Partitioning Method Based on Topological Levelization |
| title_sort | multi fpga partitioning method based on topological levelization |
| url | http://dx.doi.org/10.1155/2010/709487 |
| work_keys_str_mv | AT nabilkerkiz multifpgapartitioningmethodbasedontopologicallevelization AT amrelchouemi multifpgapartitioningmethodbasedontopologicallevelization AT donbouldin multifpgapartitioningmethodbasedontopologicallevelization |