Implementation of Simplified Data Encryption Standard on FPGA using VHDL
In recent years, dramatic changed has been made in communication sector. Due to enormous development in communication devices, globally internet-connected network largely used in all human activities. The security of information has been becoming a major concern for all users and clients, whom depen...
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| Format: | Article |
| Language: | English |
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Sulaimani Polytechnic University
2022-03-01
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| Series: | Kurdistan Journal of Applied Research |
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| Online Access: | https://www.kjar.spu.edu.iq/index.php/kjar/article/view/711 |
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| author | salim Qadir Mohammed |
| author_facet | salim Qadir Mohammed |
| author_sort | salim Qadir Mohammed |
| collection | DOAJ |
| description | In recent years, dramatic changed has been made in communication sector. Due to enormous development in communication devices, globally internet-connected network largely used in all human activities. The security of information has been becoming a major concern for all users and clients, whom depend on network system. The cryptography has played significant role to combat these challenges and improve confidentiality, integrity, and authentication of data communication in the network. The Data Encryption Standard (DES) is one of most familiar type of cryptography and widely used in the modern network system, which has been adopted in encryption and decryption a digital information for several decades. The DES is replaced by a number of new cryptographical methods, which based on DES, like AES and 3DES. In the same time some hardware tools have gained a lot of attention and become interested for researchers and academics to design and implement their model proposals with these hardware-based tools. Therefore, this paper, shows the design of a Simplified Data Encryption Standard (S-DES) by using VHDL language. The design is synthesized, compiled and implemented on the FPGA Altera board, which, consists Quartus II software environment, and Altera Cyclone IV 4CX150FPGA device. The S-DES has been successfully implemented with few numbers of logic elements.
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| format | Article |
| id | doaj-art-eac77e93858e4598a338a39266811741 |
| institution | Kabale University |
| issn | 2411-7684 2411-7706 |
| language | English |
| publishDate | 2022-03-01 |
| publisher | Sulaimani Polytechnic University |
| record_format | Article |
| series | Kurdistan Journal of Applied Research |
| spelling | doaj-art-eac77e93858e4598a338a392668117412025-02-11T21:00:14ZengSulaimani Polytechnic UniversityKurdistan Journal of Applied Research2411-76842411-77062022-03-017110.24017/Science.2022.1.2711Implementation of Simplified Data Encryption Standard on FPGA using VHDLsalim Qadir Mohammed0Communication Department Technical College of Engineering Sulaimani Polytechnic University Sulaimani, IraqIn recent years, dramatic changed has been made in communication sector. Due to enormous development in communication devices, globally internet-connected network largely used in all human activities. The security of information has been becoming a major concern for all users and clients, whom depend on network system. The cryptography has played significant role to combat these challenges and improve confidentiality, integrity, and authentication of data communication in the network. The Data Encryption Standard (DES) is one of most familiar type of cryptography and widely used in the modern network system, which has been adopted in encryption and decryption a digital information for several decades. The DES is replaced by a number of new cryptographical methods, which based on DES, like AES and 3DES. In the same time some hardware tools have gained a lot of attention and become interested for researchers and academics to design and implement their model proposals with these hardware-based tools. Therefore, this paper, shows the design of a Simplified Data Encryption Standard (S-DES) by using VHDL language. The design is synthesized, compiled and implemented on the FPGA Altera board, which, consists Quartus II software environment, and Altera Cyclone IV 4CX150FPGA device. The S-DES has been successfully implemented with few numbers of logic elements. https://www.kjar.spu.edu.iq/index.php/kjar/article/view/711Cryptography, DES, S-DES, FPGA, VHDL |
| spellingShingle | salim Qadir Mohammed Implementation of Simplified Data Encryption Standard on FPGA using VHDL Kurdistan Journal of Applied Research Cryptography, DES, S-DES, FPGA, VHDL |
| title | Implementation of Simplified Data Encryption Standard on FPGA using VHDL |
| title_full | Implementation of Simplified Data Encryption Standard on FPGA using VHDL |
| title_fullStr | Implementation of Simplified Data Encryption Standard on FPGA using VHDL |
| title_full_unstemmed | Implementation of Simplified Data Encryption Standard on FPGA using VHDL |
| title_short | Implementation of Simplified Data Encryption Standard on FPGA using VHDL |
| title_sort | implementation of simplified data encryption standard on fpga using vhdl |
| topic | Cryptography, DES, S-DES, FPGA, VHDL |
| url | https://www.kjar.spu.edu.iq/index.php/kjar/article/view/711 |
| work_keys_str_mv | AT salimqadirmohammed implementationofsimplifieddataencryptionstandardonfpgausingvhdl |