An 8-Channel Phased-Array CMOS Transmitter for 5G+ Application
This paper presents a new 8-channel phased-array transmitter (8-CPA TX) integrated with a 10 GHz in-phase quadrature-phase (I/Q) local oscillator generator. The 8-CPA TX comprises three functionally defined subsidiary blocks—a delay-locked loop (DLL), a frequency multiplier (FM), and an 8-channel ph...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
The Korean Institute of Electromagnetic Engineering and Science
2025-07-01
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| Series: | Journal of Electromagnetic Engineering and Science |
| Subjects: | |
| Online Access: | https://www.jees.kr/upload/pdf/jees-2025-4-r-306.pdf |
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| Summary: | This paper presents a new 8-channel phased-array transmitter (8-CPA TX) integrated with a 10 GHz in-phase quadrature-phase (I/Q) local oscillator generator. The 8-CPA TX comprises three functionally defined subsidiary blocks—a delay-locked loop (DLL), a frequency multiplier (FM), and an 8-channel phase shifter. The DLL produces uniformly delayed 256-phase pulses when locked. When an external 156.25 MHz oscillator is applied as a reference clock, fIF is up-converted to 10 GHz by the FM. Combining the DLL and the FM in the cascade demonstrates compelling RMS jitter performance, with an integrated jitter of 72 fs from 12 kHz to 20 MHz. This is comparable to the RMS jitter of the reference clock and enables accurate I/Q signal generation. A capacitive ladder-type passive amplitude modulator (AM) is invented to implement a direct binary to millimeter wave phase shift modulation. Significant power consumption reduction is accomplished because of the no-power consumption of the AM. The proposed 8-CPA TX is implemented on the TSMC 65-nm CMOS process, with an area of 2 mm2. |
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| ISSN: | 2671-7255 2671-7263 |