RTL development of a parameterizable Reed–Solomon Codec
Abstract Error correction coding (ECC) methods have been considered essential constituents of data transmission systems. Reed–Solomon (RS) codes are a core ECC technique that have been adopted in numerous applications and standards. Several register‐transfer level (RTL) architectures for RS codecs h...
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| Format: | Article |
| Language: | English |
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Wiley
2021-03-01
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| Series: | IET Computers & Digital Techniques |
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| Online Access: | https://doi.org/10.1049/cdt2.12009 |
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| author | Mateus G. Silva Guilherme L. Silvano Ricardo O. Duarte |
| author_facet | Mateus G. Silva Guilherme L. Silvano Ricardo O. Duarte |
| author_sort | Mateus G. Silva |
| collection | DOAJ |
| description | Abstract Error correction coding (ECC) methods have been considered essential constituents of data transmission systems. Reed–Solomon (RS) codes are a core ECC technique that have been adopted in numerous applications and standards. Several register‐transfer level (RTL) architectures for RS codecs have been proposed to address specific demands and overcome scalability challenges in speed and area. However, the influence of the main RS codec parameters on the corresponding hardware design has been undervalued by literature. The authors propose an open access intellectual property (IP) of a parameterizable RS codec and explore key aspects of its RTL development using IEEE 802.15.7 standard as illustration. Herein, it is demonstrated that formal verification has the potential to be solely used to attest the correctness of the developed IP for the RS codec configurations specified by IEEE 802.15.7. Furthermore, synthesis reports for the target field‐programmable gate array devices indicate that the proposed IP is able to cope with throughput requirements in IEEE 802.15.7. |
| format | Article |
| id | doaj-art-e98f15dc5f684b1d8a552c35fdc67389 |
| institution | DOAJ |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2021-03-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj-art-e98f15dc5f684b1d8a552c35fdc673892025-08-20T03:21:10ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-03-0115214315910.1049/cdt2.12009RTL development of a parameterizable Reed–Solomon CodecMateus G. Silva0Guilherme L. Silvano1Ricardo O. Duarte2Graduate Program in Electrical Engineering Universidade Federal de Minas Gerais Belo Horizonte Minas Gerais BrazilGraduate Program in Electrical Engineering Universidade Federal de Minas Gerais Belo Horizonte Minas Gerais BrazilGraduate Program in Electrical Engineering Universidade Federal de Minas Gerais Belo Horizonte Minas Gerais BrazilAbstract Error correction coding (ECC) methods have been considered essential constituents of data transmission systems. Reed–Solomon (RS) codes are a core ECC technique that have been adopted in numerous applications and standards. Several register‐transfer level (RTL) architectures for RS codecs have been proposed to address specific demands and overcome scalability challenges in speed and area. However, the influence of the main RS codec parameters on the corresponding hardware design has been undervalued by literature. The authors propose an open access intellectual property (IP) of a parameterizable RS codec and explore key aspects of its RTL development using IEEE 802.15.7 standard as illustration. Herein, it is demonstrated that formal verification has the potential to be solely used to attest the correctness of the developed IP for the RS codec configurations specified by IEEE 802.15.7. Furthermore, synthesis reports for the target field‐programmable gate array devices indicate that the proposed IP is able to cope with throughput requirements in IEEE 802.15.7.https://doi.org/10.1049/cdt2.12009codecserror correction codesfield programmable gate arraysformal verificationIEEE standardsReed‐Solomon codes |
| spellingShingle | Mateus G. Silva Guilherme L. Silvano Ricardo O. Duarte RTL development of a parameterizable Reed–Solomon Codec IET Computers & Digital Techniques codecs error correction codes field programmable gate arrays formal verification IEEE standards Reed‐Solomon codes |
| title | RTL development of a parameterizable Reed–Solomon Codec |
| title_full | RTL development of a parameterizable Reed–Solomon Codec |
| title_fullStr | RTL development of a parameterizable Reed–Solomon Codec |
| title_full_unstemmed | RTL development of a parameterizable Reed–Solomon Codec |
| title_short | RTL development of a parameterizable Reed–Solomon Codec |
| title_sort | rtl development of a parameterizable reed solomon codec |
| topic | codecs error correction codes field programmable gate arrays formal verification IEEE standards Reed‐Solomon codes |
| url | https://doi.org/10.1049/cdt2.12009 |
| work_keys_str_mv | AT mateusgsilva rtldevelopmentofaparameterizablereedsolomoncodec AT guilhermelsilvano rtldevelopmentofaparameterizablereedsolomoncodec AT ricardooduarte rtldevelopmentofaparameterizablereedsolomoncodec |