Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters
Running max/min filters on rectangular kernels are widely used in many digital signal and image processing applications. Filtering with a k×k kernel requires of k2−1 comparisons per sample for a direct implementation; thus, performance scales expensively with the kernel size k. Faster computations...
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| Format: | Article |
| Language: | English |
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Wiley
2013-01-01
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| Series: | The Scientific World Journal |
| Online Access: | http://dx.doi.org/10.1155/2013/108103 |
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| _version_ | 1832566580428406784 |
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| author | Cesar Torres-Huitzil |
| author_facet | Cesar Torres-Huitzil |
| author_sort | Cesar Torres-Huitzil |
| collection | DOAJ |
| description | Running max/min filters on rectangular kernels are widely used in many digital signal and image processing applications. Filtering with a k×k kernel requires of k2−1 comparisons per sample for a direct implementation; thus, performance scales expensively with the kernel size k. Faster computations can be achieved by kernel decomposition and using constant time one-dimensional algorithms on custom hardware. This paper presents a hardware architecture for real-time computation of running max/min filters based on the van Herk/Gil-Werman (HGW) algorithm. The proposed architecture design uses less computation and memory resources than previously reported architectures when targeted to Field Programmable Gate Array (FPGA) devices. Implementation results show that the architecture is able to compute max/min filters, on 1024×1024 images with up to 255×255 kernels, in around 8.4 milliseconds, 120 frames per second, at a clock frequency of 250 MHz. The implementation is highly scalable for the kernel size with good performance/area tradeoff suitable for embedded applications. The applicability of the architecture is shown for local adaptive image thresholding. |
| format | Article |
| id | doaj-art-e4e4962eab4b4633bb3389e2bd7b8458 |
| institution | Kabale University |
| issn | 1537-744X |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | The Scientific World Journal |
| spelling | doaj-art-e4e4962eab4b4633bb3389e2bd7b84582025-02-03T01:03:51ZengWileyThe Scientific World Journal1537-744X2013-01-01201310.1155/2013/108103108103Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min FiltersCesar Torres-Huitzil0Information Technology Laboratory, CINVESTAV, Km. 5.5 Carretera Ciudad Victoria-Soto La Marina, 87130 Ciudad Victoria, TAMPS, MexicoRunning max/min filters on rectangular kernels are widely used in many digital signal and image processing applications. Filtering with a k×k kernel requires of k2−1 comparisons per sample for a direct implementation; thus, performance scales expensively with the kernel size k. Faster computations can be achieved by kernel decomposition and using constant time one-dimensional algorithms on custom hardware. This paper presents a hardware architecture for real-time computation of running max/min filters based on the van Herk/Gil-Werman (HGW) algorithm. The proposed architecture design uses less computation and memory resources than previously reported architectures when targeted to Field Programmable Gate Array (FPGA) devices. Implementation results show that the architecture is able to compute max/min filters, on 1024×1024 images with up to 255×255 kernels, in around 8.4 milliseconds, 120 frames per second, at a clock frequency of 250 MHz. The implementation is highly scalable for the kernel size with good performance/area tradeoff suitable for embedded applications. The applicability of the architecture is shown for local adaptive image thresholding.http://dx.doi.org/10.1155/2013/108103 |
| spellingShingle | Cesar Torres-Huitzil Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters The Scientific World Journal |
| title | Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters |
| title_full | Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters |
| title_fullStr | Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters |
| title_full_unstemmed | Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters |
| title_short | Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters |
| title_sort | resource efficient hardware architecture for fast computation of running max min filters |
| url | http://dx.doi.org/10.1155/2013/108103 |
| work_keys_str_mv | AT cesartorreshuitzil resourceefficienthardwarearchitectureforfastcomputationofrunningmaxminfilters |