Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural Variations
We present a novel multi-task learning (MTL) approach with shared representation for the real-time extraction of Berkeley Short-channel IGFET Model-Common Gate (BSIM-CMG) parameters in nanosheet field-effect transistors (NSFETs) with multiple structural variations. An innovative artificial neural ne...
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2024-01-01
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| Online Access: | https://ieeexplore.ieee.org/document/10781410/ |
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| author | Seunghwan Lee Seungjoon Eom Jinsu Jeong Junjong Lee Sanguk Lee Hyeok Yun Yonghwan Ahn Rock-Hyun Baek |
| author_facet | Seunghwan Lee Seungjoon Eom Jinsu Jeong Junjong Lee Sanguk Lee Hyeok Yun Yonghwan Ahn Rock-Hyun Baek |
| author_sort | Seunghwan Lee |
| collection | DOAJ |
| description | We present a novel multi-task learning (MTL) approach with shared representation for the real-time extraction of Berkeley Short-channel IGFET Model-Common Gate (BSIM-CMG) parameters in nanosheet field-effect transistors (NSFETs) with multiple structural variations. An innovative artificial neural network (ANN) architecture, coupled with specialized training strategies, was introduced to extract BSIM-CMG parameters in NSFETs with varying gate lengths (<inline-formula> <tex-math notation="LaTeX">$L_{\mathrm {g}}$ </tex-math></inline-formula>), nanosheet widths (<inline-formula> <tex-math notation="LaTeX">$W_{\mathrm {ns}}$ </tex-math></inline-formula>), and thicknesses (<inline-formula> <tex-math notation="LaTeX">$T_{\mathrm {ns}}$ </tex-math></inline-formula>). To mitigate overfitting due to disparate data sources, such as Monte Carlo simulations for training data and technology computer-aided design (TCAD) simulations or hardware measurements for test data, additive noise was incorporated into the training data. Optimal test accuracy was achieved with maximum noise levels of 10% for <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {d}}$ </tex-math></inline-formula> and 2% for <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gg}}$ </tex-math></inline-formula>. The MTL approach, leveraging shared representation, effectively captured relationships among input-output groups, reducing the risk of biased ANN training toward any specific group. The proposed method was evaluated using a 1.4 nm node NSFET and eight additional NSFETs with <inline-formula> <tex-math notation="LaTeX">$L_{\mathrm {g}}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$T_{\mathrm {ns}}$ </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">$W_{\mathrm {ns}}$ </tex-math></inline-formula> variations of 1, 0.5, and 5 nm, respectively, from the baseline values of 12, 5, and 25 nm at the 1.4 nm node. The MTL-based ANN successfully extracted BSIM-CMG parameters for both <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {d}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gg}}$ </tex-math></inline-formula>, yielding low relative modeling errors of 4.26% for <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {d}}$ </tex-math></inline-formula> and 0.709% for <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gg}}$ </tex-math></inline-formula>. Additionally, the method was validated using 3 nm node hardware NSFETs and nanowire FETs with varying <inline-formula> <tex-math notation="LaTeX">$L_{\mathrm {g}}$ </tex-math></inline-formula> and nanowire diameters, demonstrating its versatility across different technology nodes and device architectures. |
| format | Article |
| id | doaj-art-e45b9ce020794694a8efa134ebbd1964 |
| institution | DOAJ |
| issn | 2169-3536 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-e45b9ce020794694a8efa134ebbd19642025-08-20T02:50:41ZengIEEEIEEE Access2169-35362024-01-011218461918462810.1109/ACCESS.2024.351261210781410Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural VariationsSeunghwan Lee0https://orcid.org/0000-0003-3137-9335Seungjoon Eom1https://orcid.org/0000-0002-5743-1798Jinsu Jeong2https://orcid.org/0000-0002-0000-6416Junjong Lee3https://orcid.org/0000-0002-0513-8784Sanguk Lee4https://orcid.org/0000-0002-8932-6626Hyeok Yun5https://orcid.org/0000-0003-4597-4389Yonghwan Ahn6https://orcid.org/0009-0004-7381-8441Rock-Hyun Baek7https://orcid.org/0000-0002-6175-8101Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaWe present a novel multi-task learning (MTL) approach with shared representation for the real-time extraction of Berkeley Short-channel IGFET Model-Common Gate (BSIM-CMG) parameters in nanosheet field-effect transistors (NSFETs) with multiple structural variations. An innovative artificial neural network (ANN) architecture, coupled with specialized training strategies, was introduced to extract BSIM-CMG parameters in NSFETs with varying gate lengths (<inline-formula> <tex-math notation="LaTeX">$L_{\mathrm {g}}$ </tex-math></inline-formula>), nanosheet widths (<inline-formula> <tex-math notation="LaTeX">$W_{\mathrm {ns}}$ </tex-math></inline-formula>), and thicknesses (<inline-formula> <tex-math notation="LaTeX">$T_{\mathrm {ns}}$ </tex-math></inline-formula>). To mitigate overfitting due to disparate data sources, such as Monte Carlo simulations for training data and technology computer-aided design (TCAD) simulations or hardware measurements for test data, additive noise was incorporated into the training data. Optimal test accuracy was achieved with maximum noise levels of 10% for <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {d}}$ </tex-math></inline-formula> and 2% for <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gg}}$ </tex-math></inline-formula>. The MTL approach, leveraging shared representation, effectively captured relationships among input-output groups, reducing the risk of biased ANN training toward any specific group. The proposed method was evaluated using a 1.4 nm node NSFET and eight additional NSFETs with <inline-formula> <tex-math notation="LaTeX">$L_{\mathrm {g}}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$T_{\mathrm {ns}}$ </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">$W_{\mathrm {ns}}$ </tex-math></inline-formula> variations of 1, 0.5, and 5 nm, respectively, from the baseline values of 12, 5, and 25 nm at the 1.4 nm node. The MTL-based ANN successfully extracted BSIM-CMG parameters for both <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {d}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gg}}$ </tex-math></inline-formula>, yielding low relative modeling errors of 4.26% for <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {d}}$ </tex-math></inline-formula> and 0.709% for <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gg}}$ </tex-math></inline-formula>. Additionally, the method was validated using 3 nm node hardware NSFETs and nanowire FETs with varying <inline-formula> <tex-math notation="LaTeX">$L_{\mathrm {g}}$ </tex-math></inline-formula> and nanowire diameters, demonstrating its versatility across different technology nodes and device architectures.https://ieeexplore.ieee.org/document/10781410/Additive noiseartificial neural network (ANN)Berkeley short-channel IGFET model common multi-gate (BSIM-CMG)compact modelmulti-task learning (MTL)nanosheet field-effect transistor (NSFET) |
| spellingShingle | Seunghwan Lee Seungjoon Eom Jinsu Jeong Junjong Lee Sanguk Lee Hyeok Yun Yonghwan Ahn Rock-Hyun Baek Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural Variations IEEE Access Additive noise artificial neural network (ANN) Berkeley short-channel IGFET model common multi-gate (BSIM-CMG) compact model multi-task learning (MTL) nanosheet field-effect transistor (NSFET) |
| title | Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural Variations |
| title_full | Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural Variations |
| title_fullStr | Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural Variations |
| title_full_unstemmed | Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural Variations |
| title_short | Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural Variations |
| title_sort | multi task learning for real time bsim cmg parameter extraction of nsfets with multiple structural variations |
| topic | Additive noise artificial neural network (ANN) Berkeley short-channel IGFET model common multi-gate (BSIM-CMG) compact model multi-task learning (MTL) nanosheet field-effect transistor (NSFET) |
| url | https://ieeexplore.ieee.org/document/10781410/ |
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